Circuit Partitioning for Parallel Simulation
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Solution Overview
Problem
Current circuit simulation methods are inefficient in handling complex integrated circuits due to the need to consider parasitic effects, leading to poor simulation results and increased computational resources, especially in nanometer, gigahertz, low power VLSI design where power and signal integrity are critical.
Innovation Solution
A distributed computing approach that simulates circuits by generating a system graph, partitioning it into subtrees, and solving each subtree independently using multiple processors, allowing for parallel calculations and obtaining real solutions for the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If distributed computing is used to simulate circuits, then computation time is reduced and accuracy is improved, but device complexity increases
Solution Approach 1:
The circuit network is partitioned into multiple subtrees using graph theory algorithms. Each subtree represents an independent subcircuit that can be simulated separately. This segmentation allows the overall simulation problem to be divided into smaller, manageable pieces that can be processed in parallel, significantly reducing computation time while maintaining simulation accuracy.
Solution Approach 2:
The patent transitions from single-processor sequential simulation to multi-processor parallel simulation by adding the dimension of concurrent processing. Multiple processors work simultaneously on different subtrees, transforming the computational approach from one-dimensional sequential execution to multi-dimensional parallel execution, thereby reducing computation time without proportionally increasing system complexity.
2Measurement precision
If more parasitic effects are considered in simulation, then accuracy is improved, but computational resources and complexity increase
Solution Approach 1:
By partitioning the complex circuit network into smaller subtrees, the patent enables accurate inclusion of parasitic effects within each subtree without overwhelming the computational system. The segmentation isolates the complexity of parasitic interactions to local levels while maintaining global accuracy, allowing detailed modeling of parasitic resistances, inductances, and capacitances without proportionally increasing overall computational burden.
3Device complexity
If single-machine simulation is used for complex circuits, then device complexity is minimized, but computation time increases and accuracy decreases
Solution Approach 1:
The patent introduces parallel processing as an additional dimension to circuit simulation. By distributing the simulation of different subtrees across multiple processors working concurrently, the system achieves faster computation times for complex circuits without requiring a proportional increase in single-machine complexity. This dimensional transition from sequential to parallel processing resolves the trade-off between system complexity and computation time.
Data Source
AI summary
A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.