Circuit Verification Pattern Matching with Sub-Structure Validation

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Solution Overview

Problem

Verification tools in integrated circuit design struggle to detect variations of approved design patterns, leading to time-intensive manual error waiver processes, as they match specific structural patterns rather than functionality, and fail to recognize variations as verified.

Innovation Solution

Implementing a method that searches for both base and sub-patterns in circuit descriptions, with sub-patterns validated based on predetermined rules to minimize reported errors, allowing for precise handling and control over the verification tool's output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If verification tools match specific structural patterns, then verification precision is improved, but variations of approved patterns are not detected and cause false errors

Engineering Contradiction:

Improvepattern matching precisionVSAvoidpattern variation recognition

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The verification tool dynamically adjusts its pattern matching approach by first searching for base patterns and then automatically identifying and validating sub-patterns. This dynamic two-stage process allows the tool to adapt to variations of approved patterns while maintaining precision in detecting the core design intent.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent segments the pattern matching process into two distinct phases: base pattern matching and sub-pattern validation. This segmentation allows the verification tool to handle both exact matches and variations systematically, reducing false errors while maintaining verification precision.

Inventive Principle:

Principle #1Segmentation

2Reliability

If verification tools report all pattern mismatches, then verification thoroughness is improved, but manual error waiver time increases significantly

Engineering Contradiction:

Improveverification thoroughnessVSAvoidmanual error waiver time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The verification tool performs self-validation by automatically checking whether detected sub-patterns match approved base patterns. This self-service capability allows the tool to autonomously validate variations of approved patterns and suppress false errors, significantly reducing the need for manual error waiver while maintaining thorough verification.

Inventive Principle:

Principle #25Self-service

3Productivity

If verification tools use predetermined base patterns, then verification speed is improved, but variations of base patterns are not recognized as verified

Engineering Contradiction:

Improveverification speedVSAvoidpattern variation acceptance

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements preliminary action by first establishing a library of approved base patterns before verification begins. During verification, the tool quickly matches circuits against these pre-defined base patterns and then automatically extends validation to their sub-patterns, maintaining high verification speed while accepting pattern variations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9886753B2Verification of circuit structures including sub-structure variants

Publication Date: 2018.02.06 SYNOPSYS INC

AI summary

A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.