Incremental Circuit Placement for Timing Optimization
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Solution Overview
Problem
Conventional circuit design optimization techniques often result in suboptimal performance in certain regions due to global optimization approaches, leading to time-consuming iterative processes between re-synthesis and placement to meet timing requirements, especially when prioritizing wire length over timing characteristics.
Innovation Solution
The method involves identifying critical regions within a circuit design, re-synthesizing and re-locating blocks within those regions using placement techniques that prioritize timing, while maintaining the functionality and connectivity defined by input and output blocks, allowing for incremental optimization without re-synthesizing or re-placing the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If global optimization is performed on the entire circuit design during physical synthesis, then wire length is reduced and routing resources are conserved, but timing characteristics deteriorate in certain regions
Solution Approach 1:
The patent divides the circuit design into hierarchical levels (levels 0-3) based on connectivity distance from input blocks. This segmentation allows different placement strategies to be applied at different levels: Level 0 handles critical timing regions with dedicated optimization, while Levels 1-3 handle progressively less critical regions. This resolves the contradiction by preventing global optimization from uniformly prioritizing wire length at the expense of timing in critical regions.
Solution Approach 2:
The patent applies different optimization criteria to different regions of the circuit design. Critical regions (Level 0) near input blocks are optimized for timing characteristics with stricter constraints, while non-critical regions (Levels 1-3) are optimized for wire length. This local differentiation resolves the contradiction by allowing timing to be prioritized where it matters most while conserving routing resources in less critical areas.
2Reliability
If multiple iterations between re-synthesis and place and route tools are performed to meet timing requirements, then timing characteristics improve, but productivity deteriorates due to time consumption
Solution Approach 1:
The patent performs preliminary placement of blocks at multiple hierarchical levels before final routing. By pre-positioning blocks in their target sites based on connectivity analysis and level assignment, the system reduces the need for multiple iterative re-synthesis and re-placement cycles. This preliminary organization of blocks by connectivity level allows timing-critical regions to be optimized upfront, reducing iteration count and improving productivity.
Solution Approach 2:
The patent applies placement optimization selectively to specific levels and regions rather than uniformly across the entire circuit design. Level 0 (critical timing region) receives exhaustive optimization attention, while Levels 1-3 receive progressively less intensive optimization. This partial action approach meets timing requirements for critical regions without unnecessarily consuming time optimizing non-critical regions, thus improving productivity.
3Reliability
If blocks are assigned to sites based on connectivity levels, then timing characteristics improve in critical regions, but device complexity increases due to multi-level placement methodology
Solution Approach 1:
The patent segments the placement methodology into four distinct levels (0-3) based on connectivity distance from input blocks. Each level has specific placement criteria: Level 0 for timing-critical blocks directly connected to input blocks, Level 1 for blocks connected to Level 0, Level 2 for blocks connected to Level 1, and Level 3 for remaining blocks. This structured segmentation makes the complex multi-level process systematic and manageable, resolving the contradiction by organizing complexity into repeatable patterns rather than arbitrary complexity.
Data Source
AI summary
A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.