Circuit Power Estimation Using Structural Template Matching
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Solution Overview
Problem
Current power estimation methods for circuit designs in programmable ICs are inaccurate due to designer estimation errors and inability to account for variability in toggle rates, leading to time-consuming and costly full implementation to determine actual power consumption.
Innovation Solution
A method that involves matching circuit elements to pre-characterized structural templates with associated toggle rates to estimate power consumption, using a computing arrangement to determine toggle rates and calculate power consumption based on these estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If designer estimation of logic resources is used, then power estimation can be performed early in design, but accuracy of resource count is substantially inaccurate
Solution Approach 1:
The patent creates a simplified copy or model of the circuit design at the netlist level, which captures essential structural information without requiring full implementation. This model includes logic element counts and connectivity data that can be used for accurate power estimation while avoiding the time-consuming full implementation process.
Solution Approach 2:
The patent performs power estimation actions preliminarily by analyzing the netlist structure before full implementation. It extracts logic element counts and connectivity information from the netlist to calculate toggle rates and power consumption, enabling early power analysis without waiting for complete design implementation.
2Productivity
If generic global toggle rate defaults are used, then power estimation can be performed quickly, but accuracy fails to account for variability within design
Solution Approach 1:
The patent applies local quality by determining toggle rates for different logic elements individually based on their specific connectivity and position in the circuit, rather than using a single global default value. It analyzes the netlist to identify which logic elements are driven by clock signals and calculates local toggle rates that reflect actual design variability.
Solution Approach 2:
The patent changes the parameter approach from using fixed global default toggle rates to dynamically calculated toggle rates based on netlist analysis. It determines toggle rates as a function of clock frequency and the specific connectivity of each logic element, allowing parameters to adapt to local design characteristics.
3Measurement precision
If full design implementation is completed to determine power consumption, then accurate power measurement is achieved, but process becomes time-consuming and costly
Solution Approach 1:
The patent extracts only the essential information needed for power estimation from the full design - specifically logic element counts and connectivity data from the netlist. It separates these critical parameters from the complete implementation process, obtaining sufficient data for accurate power analysis without requiring full design completion.
4Loss of time
If designer estimates of toggle rates are used, then power estimation can be performed early, but accuracy is quite inaccurate relative to actual toggle rates
Solution Approach 1:
The patent incorporates feedback by using actual netlist structure and connectivity information to refine toggle rate estimates. Instead of relying on designer guesses, it analyzes the real circuit topology to determine which logic elements are clocked and calculates toggle rates based on actual design characteristics, providing feedback-driven accuracy improvement.
Data Source
AI summary
Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to structural templates. Each structural template is representative of one or more circuit elements and has associated information descriptive of one or more toggle rates. Respective estimated toggle rates are determined for the circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates. An estimated power consumption level is determined as a function of the estimated toggle rates of the circuit elements, and data indicative of the estimated power consumption level is output.