Circuit Power Analysis Using Netlist Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power simulation methods for microchips are computationally expensive and only feasible for circuits with a few hundred devices or a small set of input stimuli, making them inefficient for simulating power consumption in modern microchips with increasing transistor densities.
Innovation Solution
A divide-and-conquer approach is adopted by partitioning the circuit into smaller blocks, generating circuit logic models in hardware description language, and using a combination of logic and circuit simulators to calculate power consumption, which reduces computational resources required for simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If flat-mode simulation using modern circuit simulators is used, then power consumption simulation accuracy is maintained, but computational expense increases significantly making it infeasible for circuits with millions of transistors
Solution Approach 1:
The circuit netlist is partitioned into multiple circuit blocks, each processed independently by the simulator. This segmentation allows the total computational expense to be distributed across multiple smaller simulations rather than one large simulation, making power analysis feasible for circuits with millions of transistors while maintaining accuracy through comprehensive input stimulus coverage.
2Measurement precision
If comprehensive input stimuli are used for simulation, then power consumption analysis completeness is improved, but simulation time increases significantly
Solution Approach 1:
The circuit is divided into blocks that can be processed in parallel or sequentially with optimized stimulus application. This allows comprehensive power analysis across all circuit blocks while reducing total simulation time through efficient resource utilization and avoiding redundant computations across the entire circuit.
Solution Approach 2:
Circuit blocks are pre-processed and characterized before full power simulation. This preliminary action includes identifying critical paths, grouping similar blocks, and preparing optimized stimulus sets, which reduces the overall simulation time required for comprehensive power analysis.
Data Source
AI summary
A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.