Circuit Design Prediction Model Updates

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Solution Overview

Problem

Traditional design-process interfaces for integrated circuits struggle to capture manufacturing variations in smaller geometries and complex process stacks, leading to issues like CMP and etch failures, which can result in unmanufacturable designs and require significant computational resources for prediction analysis.

Innovation Solution

A method and system that allow for efficient updating of model predictions by abstracting model parameter information into a smaller database, enabling multiple designers to work independently and share updates, reducing the need for full geometric data distribution and facilitating collaborative design while performing incremental model parameter analyses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If full geometric data is distributed to all designers for prediction analysis, then prediction accuracy is improved, but computational resources and data distribution complexity increase significantly

Engineering Contradiction:
Improveprediction accuracyVSAvoiddata distribution complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the full-chip prediction task into block-level predictions. Each designer works on a specific block and performs prediction analysis only for that block, rather than distributing and analyzing complete full-chip geometric data. This segmentation reduces data distribution complexity while maintaining prediction accuracy for each block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts only the necessary geometric parameters for prediction analysis from the full geometric data. Instead of distributing complete geometric information, the system extracts and distributes only the parameters needed for CMP and etch prediction, reducing data volume and distribution complexity while preserving prediction accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If full-chip reanalysis is performed for every design update, then prediction accuracy is maintained, but productivity and time-to-volume decrease

Engineering Contradiction:
Improveprediction accuracyVSAvoiddesign update efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent enables incremental updates by segmenting the prediction analysis into block-level operations. When a designer updates a block, only that block's prediction is reanalyzed rather than performing a complete full-chip reanalysis. This maintains prediction accuracy for updated blocks while significantly improving productivity during design iterations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs prediction analysis at the block level during the design process itself, rather than waiting for complete design finalization. This preliminary action allows designers to identify and correct CMP and etch issues early in the design phase, improving productivity by avoiding late-stage redesigns.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple designers work independently on different blocks, then collaboration efficiency is improved, but maintaining consistent prediction models across blocks becomes more difficult

Engineering Contradiction:
Improvecollaboration efficiencyVSAvoidmodel consistency
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent implements a universal prediction model that can be applied consistently across all blocks. The same CMP and etch prediction algorithms and parameters are used for every block, ensuring model consistency. This universal approach allows multiple designers to work independently on different blocks while maintaining consistent prediction standards throughout the entire chip.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent establishes a feedback mechanism where prediction results from individual blocks are aggregated and used to update the overall chip-level prediction model. This feedback loop ensures that local block predictions remain consistent with the global chip model, maintaining model stability while allowing independent block-level design work.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8806396B2Method and system performing circuit design predictions
Publication Date: 2014.08.12 CADENCE DESIGN SYST INC
  • US8806396B2 patent drawing
  • US8806396B2 patent drawing
  • US8806396B2 patent drawing

AI summary

Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).