Circuit Design Property Ranking via Static Analysis
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Solution Overview
Problem
The complexity of circuit design verification leads to an overwhelming number of automatically generated properties, many of which are redundant or of little use, wasting computing resources and extending verification time, as current techniques lack effective methods to rank and prioritize these properties.
Innovation Solution
A tool that generates circuit design properties from signal traces and uses static analysis to rank them based on their validity, presenting only the most valuable properties to the designer for further testing, thereby optimizing the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all automatically generated properties are tested against the circuit design, then comprehensive verification coverage is achieved, but computing resources are wasted and verification time is extended
Solution Approach 1:
The patent changes the parameter of property evaluation from binary (true/false) to a ranked scale based on validation difficulty. By assigning ranks according to how difficult it is to prove each property true, the system prioritizes properties that are harder to validate, ensuring comprehensive coverage while reducing time spent on easily verifiable properties.
Solution Approach 2:
The patent performs preliminary static analysis to determine the truth value of each generated property before full verification testing. This preliminary action identifies and eliminates false properties and ranks true properties by validation difficulty, allowing the verification process to focus only on the most critical properties.
2Loss of information
If all automatically generated properties are presented to the circuit designer, then complete property information is provided, but the circuit designer is overwhelmed
Solution Approach 1:
The patent transforms the presentation format from a flat list of all properties to a ranked hierarchy based on validation difficulty. Properties are displayed in order of importance, with the most difficult-to-validate properties appearing first, making it easy for designers to prioritize their review while still having access to complete property information if needed.
Solution Approach 2:
The patent extracts and separates properties based on their validation characteristics, pulling out the most critical properties (those hardest to prove true) for prominent display. This extraction allows designers to focus on the most important properties while the system maintains the ability to access the complete set.
3Measurement precision
If static analysis is performed on all generated properties, then accurate rankings are determined, but computational resources are consumed
Solution Approach 1:
The patent changes the approach from uniform deep analysis of all properties to differentiated analysis based on initial assessment. Static analysis is performed to determine truth values and ranks, but the system is designed to stop analysis when sufficient ranking information is obtained, avoiding unnecessary computational expenditure on properties that will not affect the final ranking.
Data Source
AI summary
Tools for ranking of generated properties are described. A plurality of circuit design properties are generated from a signal trace of the circuit design. A static analysis of the circuit design properties is performed against one or more circuit design constraints to determine whether the properties are true. Rankings for the circuit design properties are determined responsive to results of the static analysis. The ranking for a circuit design property represents a value of the circuit design property in validating correct functionality of the circuit design. At least some of the circuit design properties are presented in a user interface responsive to the rankings for the circuit design properties.