Hierarchical Pushdown of Circuit Structures for Concurrent IC Design
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Solution Overview
Problem
Conventional physical design techniques for integrated circuits require sequential and time-consuming design efforts across hierarchical levels, leading to lengthy design cycles and inefficient resource use, as lower-level designs are constrained by and dependent on higher-level changes.
Innovation Solution
A computer-implemented method for generating pushdown structures, allowing top-level and low-level design phases to commence concurrently by performing logical and physical pushdowns of circuit structures, enabling concurrent design phases and efficient resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential hierarchical design techniques are used, then design hierarchy and structure are maintained, but design cycle time becomes excessively long and resource efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by performing logical pushdown of circuit structures from top-level to low-level hierarchies before physical design begins. This advance preparation of the logical structure enables lower-level design teams to start their work earlier without waiting for complete top-level verification, thereby reducing overall design cycle time while maintaining hierarchical integrity.
Solution Approach 2:
The patent segments the design process into distinct logical pushdown and physical pushdown phases, allowing different hierarchical levels to be designed and verified in parallel. By dividing the monolithic sequential process into separable stages that can overlap, the system achieves faster overall throughput without sacrificing design quality or hierarchical constraints.
2Productivity
If top-level design is completed and verified before low-level design begins, then design hierarchy and constraint propagation are maintained, but design resource utilization becomes inefficient
Solution Approach 1:
The patent introduces an intermediary logical pushdown structure that acts as a bridge between top-level and low-level designs. This intermediate representation allows constraint propagation and coordination between hierarchical levels without requiring complete top-level verification before low-level work begins, enabling better resource utilization while managing hierarchical complexity through structured intermediation.
3Productivity
If sequential design phases are used across hierarchical levels, then design control and verification are simplified, but overall design throughput and efficiency deteriorate
Solution Approach 1:
The patent performs preliminary logical pushdown and verification of circuit structures before physical design begins. This advance logical verification ensures design correctness is established early, allowing subsequent physical design phases to proceed in parallel with maintained verification reliability, thereby increasing overall throughput without sacrificing quality control.
Data Source
AI summary
A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.