Circuit Register Reset Optimization via ODC Analysis
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Solution Overview
Problem
Complex circuit designs often result in redundant resets for registers, leading to reduced Quality of Result (QoR) due to increased control sets, which restrict placement and lead to lower achievable clock frequencies.
Innovation Solution
The method involves generating Observability Don't Care (ODC) expressions for registers, determining redundant reset pins by checking ODC expressions on a per-cube and per-literal basis, and modifying the circuit design by connecting redundant reset pins to constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reset control signals are applied to significantly more registers than required, then reliability is improved by preventing erroneous behavior from uninitialized registers, but device complexity increases due to a large number of control sets
Solution Approach 1:
The patent extracts and removes redundant reset control signals from the circuit design by analyzing ODC expressions to identify registers that do not require resets. This extraction process eliminates unnecessary control signals while maintaining reliability for registers that actually need resets, thereby reducing the overall number of control sets and device complexity.
Solution Approach 2:
The patent changes the parameter of reset signal application by using formal verification methods to determine the precise conditions under which resets are needed. By analyzing ODC expressions and changing from a conservative approach (applying resets to all registers) to a precise approach (applying resets only where needed), the patent reduces control set complexity while maintaining reliability.
2Reliability
If a large number of control sets are used to ensure proper reset control, then reliability is improved, but productivity decreases due to restrictions in placing the circuit design on target IC
Solution Approach 1:
By extracting and removing redundant reset signals through ODC analysis, the patent reduces the number of control sets, thereby eliminating placement restrictions and improving productivity in implementing the circuit design on target IC without compromising reliability.
Solution Approach 2:
The patent applies the principle of partial action by providing resets only to the specific subset of registers that require them, rather than applying resets excessively to all registers. This partial application of reset control reduces the number of control sets and improves implementation productivity.
3Reliability
If many registers are assigned to different control sets with reset signals, then reliability is improved, but speed decreases due to lower achievable clock frequency
Solution Approach 1:
The patent extracts redundant reset signals that were unnecessarily limiting clock frequency. By removing these redundant control signals through ODC analysis, the patent allows for higher achievable clock frequencies while maintaining reliability through precise reset application where needed.
Data Source
AI summary
Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.