Circuit Resource Estimation via Module Segmentation
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Solution Overview
Problem
The complexity of capturing hardware system descriptions in synthesizable languages makes it time-consuming for designers to optimize circuit designs, particularly in programmable logic devices, due to limited feedback and correlation between source code and hardware, which hinders resource management and design efficiency.
Innovation Solution
A method is developed to generate data for estimating resource requirements by identifying intermediate circuit modules, elaborating them according to parameter sets, and storing resource estimates in tables or equations, enabling early feedback on resource needs and performance characteristics for circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If high-level languages are used to describe complex hardware systems, then the design cycle is compressed and time-to-market is shortened, but limited feedback and correlation between source code and hardware make it difficult to optimize designs
Solution Approach 1:
The patent implements feedback by providing resource estimation information back to the user during the design process. The system analyzes the netlist, estimates resource requirements for different parameter sets, and presents this feedback to help users optimize their high-level code before full implementation, thus resolving the information loss problem while maintaining the benefits of HLLs.
Solution Approach 2:
The patent performs preliminary resource estimation analysis before full implementation. By elaborating intermediate circuit modules and generating resource estimates early in the design process, the system provides actionable feedback that allows users to optimize their designs before committing to full implementation, reducing both time-to-market and improving optimizability.
2Measurement precision
If implementation tools are run to determine resource requirements for programmable logic devices, then accurate resource estimates are obtained, but significant run times require costly engineering time and cause delays
Solution Approach 1:
The patent applies partial action by performing resource estimation on a subset of the full design - specifically on intermediate circuit modules extracted from the netlist. This partial analysis provides sufficiently accurate resource estimates without requiring the time-consuming full implementation process, thus resolving the contradiction between accuracy and time consumption.
Solution Approach 2:
The patent segments the circuit design into intermediate circuit modules that can be analyzed independently. By breaking down the full design into manageable modules and estimating resources for each, the system achieves accurate resource prediction without the computational burden of analyzing the entire design through full implementation tools.
3Adaptability or versatility
If many different programmable logic devices are available to users, then device selection flexibility is increased, but it becomes difficult to determine which device is most appropriate for a given circuit design
Solution Approach 1:
The patent provides feedback by comparing resource requirements against the capabilities of different programmable logic devices. The system presents resource estimation data that enables users to systematically evaluate which device from the available options is most appropriate for their specific circuit design, thus managing the complexity of device selection while maintaining flexibility.
Data Source
AI summary
A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.


