Digital Circuit Robustness Verification via Random State Recovery

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Solution Overview

Problem

The existing methods lack a reliable way to evaluate the robustness of digital circuits, particularly their ability to recover from error states and generate correct output signals, as the recovery capability is often unknown.

Innovation Solution

A digital circuit robustness verification method and system that sets internal and external storage circuits to store random values, configures the circuit under test to perform a predetermined function, and determines the correctness of the output signal using a next stage circuit to assess the circuit's ability to resume normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional digital circuit testing methods are used, then basic functionality can be verified, but the circuit's ability to recover from error states and generate correct output signals cannot be evaluated

Engineering Contradiction:
Improvecircuit recovery capabilityVSAvoidverification system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The verification system is divided into distinct functional modules: processing circuit for configuration, previous stage circuit for signal generation, circuit under test for evaluation, and next stage circuit for output verification. This segmentation allows comprehensive robustness testing while maintaining manageable system complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary circuits (previous stage circuit and next stage circuit) that mediate between the circuit under test and the test environment. These intermediary circuits enable the evaluation of recovery capability by providing controlled input signals and verifying output signals without requiring direct access to internal circuit states.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the circuit configuration is simplified for easier verification, then verification process becomes easier, but the ability to perform comprehensive robustness testing is reduced

Engineering Contradiction:
Improveverification process easeVSAvoidrobustness evaluation accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The circuit under test is evaluated in its actual operating context with realistic input signals from the previous stage circuit and output verification by the next stage circuit. This self-service approach allows the circuit to demonstrate its inherent robustness properties without requiring external intervention or complex test setups, achieving both ease of operation and measurement precision.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11353509B2Digital circuit robustness verification method and system
Publication Date: 2022.06.07 REALTEK SEMICON CORP
  • US11353509B2 patent drawing
  • US11353509B2 patent drawing

AI summary

A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.