Circuit Routing via Parallel Run Length Rule Blockages
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Solution Overview
Problem
Traditional circuit design routing methods face challenges in efficiently routing nets while adhering to parallel run length (PRL) rules, leading to increased runtime overhead and potential design rule violations, especially in global routing phases.
Innovation Solution
The implementation of additional routing blockages, or 'bumps,' based on PRL rules, which are modeled into a capacity map to guide global routing, allowing for earlier enforcement of spacing requirements and reducing the need for runtime checks, thereby speeding up global and detailed routing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional routing methods are used without PRL rule enforcement, then routing speed is maintained, but design rule violations occur and routing quality deteriorates
Solution Approach 1:
The patent pre-calculates and stores PRL rule violations in a lookup table before routing begins. During routing, the system simply checks this pre-computed table to determine if a route violates PRL rules, rather than performing complex real-time calculations. This preliminary preparation enables fast routing decisions while ensuring PRL rule compliance.
Solution Approach 2:
The patent divides the routing problem into two independent phases: (1) pre-computation phase where PRL rule violations are calculated and stored in lookup tables, and (2) routing phase where these tables are queried for fast decision-making. This segmentation allows each phase to be optimized independently, maintaining routing speed while ensuring rule adherence.
2Manufacturing precision
If PRL rules are enforced during detailed routing, then routing quality improves, but runtime overhead increases
Solution Approach 1:
The patent performs all PRL rule violation calculations during the pre-computation phase and stores results in lookup tables. During detailed routing, the system only needs to query these pre-computed tables, which is a simple O(1) operation. This eliminates the need for complex real-time PRL calculations during routing, significantly reducing runtime overhead while maintaining routing quality.
Solution Approach 2:
The patent creates a simplified copy of the PRL rule checking mechanism in the form of lookup tables that contain pre-computed violation information. Instead of implementing the full PRL calculation logic during routing, the system uses these copied results from pre-computation, which are much faster to access and enforce the rules efficiently.
3Manufacturing precision
If routing guides are generated without considering PRL rules, then global routing speed is maintained, but spacing requirements are violated
Solution Approach 1:
The patent pre-calculates PRL rule violations and stores them in lookup tables before global routing begins. When generating routing guides, the system queries these pre-computed tables to identify regions that would violate PRL rules, then excludes them from routing guide generation. This approach ensures spacing requirements are met while maintaining global routing speed through efficient table lookups.
Solution Approach 2:
The patent introduces lookup tables as an intermediary data structure between the PRL rules and the routing guide generation process. These tables pre-process the complex PRL rule constraints and present them in a format that can be efficiently queried during routing, acting as a mediator that translates complex rules into simple lookup operations.
Data Source
AI summary
Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.