Hierarchical Circuit Routing Tile Costing for Slew Timing
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Solution Overview
Problem
Conventional routing approaches in electronic design automation face challenges in meeting slew and timing requirements when routing nets over large circuit blocks, as they either prohibit routing over blocks, increase driver size, create feedthrough nets, or disrupt circuit block floorplans, leading to inefficiencies and resource allocation difficulties.
Innovation Solution
The system divides the area associated with a circuit block into tiles, assigns costs based on manufacturing process, metal layer, and block location, using these costs in a multi-component cost function to route nets effectively and utilize buffers to meet slew and timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If nets are routed over large circuit blocks, then routing flexibility is improved, but slew and timing requirements cannot be met
Solution Approach 1:
The patent segments the circuit block area into a grid of tiles, allowing the routing system to evaluate and control net segments individually. This segmentation enables insertion of buffers at specific tile locations along long nets routed over circuit blocks, thereby maintaining routing flexibility while meeting slew and timing requirements through controlled segmentation of the net path.
2Reliability
If routing over large blocks is prohibited, then slew and timing requirements are met, but chip unroutability increases
Solution Approach 1:
The patent applies local quality by assigning different costs to different tiles based on their characteristics (such as proximity to buffers, tile density, and routing congestion). This allows the routing algorithm to preferentially select tiles that will help meet slew and timing requirements while still permitting routing over large blocks when necessary, thus maintaining chip routability without sacrificing reliability.
3Loss of time
If driver size is increased to meet timing requirements, then timing is improved, but electron-migration problems occur
Solution Approach 1:
The patent introduces buffers as intermediary elements along long net routes over circuit blocks. These buffers act as intermediate signal regeneration points that break up long net segments, allowing the use of standard-sized drivers without electron-migration problems while still meeting timing requirements through the distributed buffering strategy.
4Reliability
If feedthrough nets are created to buffer inside blocks, then buffering is achieved, but resource allocation efficiency decreases
Solution Approach 1:
The patent enables the routing system to automatically evaluate tile costs and determine optimal buffer insertion points without requiring manual intervention or complex resource allocation procedures. The tile cost metric guides the routing algorithm to self-organize net paths that naturally utilize available buffers efficiently, reducing device complexity while meeting slew and timing requirements.
Data Source
AI summary
Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.