Circuit Design Scenario Reduction via Constraint Analysis
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Solution Overview
Problem
The increasing complexity and number of scenarios in circuit design due to smaller semiconductor geometries and multiple operational modes make it impractical to optimize integrated circuits across all possible conditions, leading to high run-time and memory overhead in existing technologies.
Innovation Solution
A method for reducing the number of scenarios by identifying a subset of scenarios where the circuit design meets design constraints, using combinatorial problems like set covering and unate covering to determine sufficient scenarios for optimization, and iteratively relaxing constraints to decrease the scenario set while maintaining robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit design optimization is performed across all possible scenarios (process corners, operational modes, temperatures, voltages), then design reliability and constraint satisfaction are improved, but computational complexity and run-time increase exponentially
Solution Approach 1:
The patent extracts and identifies a subset of critical scenarios from the complete scenario space that are sufficient to guarantee design constraint satisfaction. By taking out only the essential scenarios needed for verification, the method reduces computational complexity while maintaining reliability assurance.
Solution Approach 2:
The patent creates an abstract representation (copy) of the scenario space using mathematical models and constraint formulations. This abstract model allows the system to reason about scenario relationships and identify sufficient subsets without exhaustively analyzing every concrete scenario instance.
2Productivity
If the number of scenarios is reduced to improve computational efficiency, then run-time and memory requirements decrease, but the risk of missing critical design violations increases
Solution Approach 1:
The patent implements a feedback mechanism where the scenario reduction process continuously checks whether the selected subset of scenarios provides sufficient coverage for constraint verification. The system uses constraint satisfaction feedback to iteratively refine the scenario subset, ensuring that no critical design violations are missed while maintaining computational efficiency.
Solution Approach 2:
The patent performs preliminary analysis of the scenario space before optimization to identify and eliminate redundant scenarios in advance. By pre-processing the scenario set to remove obviously equivalent or dominated scenarios, the system reduces the computational burden before the main optimization process begins.
3Adaptability or versatility
If all operational modes and process corners are considered in optimization, then design robustness across varying conditions is improved, but the number of required computations becomes impractical
Solution Approach 1:
The patent applies partial action by considering only the necessary portion of the scenario space required to achieve robust design verification. Instead of exhaustively analyzing all operational modes and process corners, the method identifies a sufficient subset that provides adequate coverage for ensuring design robustness under varying conditions.
Solution Approach 2:
The patent segments the complete scenario space into distinct groups based on operational modes, process corners, and environmental conditions. This segmentation allows the system to analyze and optimize for each segment separately, reducing the overall computational burden while maintaining comprehensive robustness verification.
Data Source
AI summary
Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of scenarios. The system can then determine a subset of scenarios based at least on the values of the constrained objects, so that if the circuit design meets design constraints in each scenario in the subset of scenarios, the circuit design is expected to meet the design constraints in each scenario in the set of scenarios.