Circuit Design SEU Susceptibility Mitigation via Segmentation
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Solution Overview
Problem
Integrated circuit designs are susceptible to single event upsets (SEUs) due to energetic particles, which can cause unintended state changes, leading to errors and system faults, and existing mitigation techniques like triplication are not always feasible due to constraints on size, power consumption, and complexity.
Innovation Solution
A computer-implemented method that determines the susceptibility level of circuit designs to SEUs, selectively applies mitigation techniques to specific regions based on calculated costs and susceptibility levels, and iteratively applies these techniques until the circuit design meets a target susceptibility level, allowing for region-by-region processing and partitioning to reduce overall susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplication mitigation technique is applied to the entire circuit design, then reliability against SEUs is improved, but device complexity and size increase excessively
Solution Approach 1:
The circuit design is divided into multiple regions, and the SEU susceptibility assessment and mitigation application is performed selectively on specific regions rather than the entire circuit. This segmentation allows mitigation to be applied only where needed, reducing overall complexity while maintaining reliability in critical areas.
Solution Approach 2:
Different regions of the circuit are assessed individually for SEU susceptibility, and mitigation techniques are applied locally to regions that exceed the target susceptibility level. This local approach ensures that resources are concentrated on vulnerable areas rather than uniformly applying mitigation throughout the entire circuit.
2Reliability
If triplication mitigation technique is applied to the entire circuit design, then reliability against SEUs is improved, but power consumption increases
Solution Approach 1:
The circuit is segmented into regions with different SEU susceptibility levels. Mitigation techniques are applied only to regions that require protection, thereby reducing the total power consumption compared to applying mitigation uniformly across the entire circuit design.
Solution Approach 2:
Instead of applying full mitigation coverage to the entire circuit, the invention applies mitigation partially to only those regions that exceed the target susceptibility level. This partial action approach achieves sufficient reliability while minimizing power consumption overhead.
3Reliability
If mitigation techniques are applied to reduce SEU susceptibility, then reliability is improved, but the circuit size increases
Solution Approach 1:
The circuit design space is segmented into multiple regions, and mitigation techniques are applied selectively to specific regions rather than the entire circuit. This reduces the total area occupied by mitigation structures while maintaining reliability in vulnerable regions.
Solution Approach 2:
Mitigation structures are placed locally in regions that exhibit high SEU susceptibility. This localized placement minimizes the overall area increase compared to uniform mitigation coverage, as protection is concentrated only where needed.
Data Source
AI summary
A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.