Circuit Design Simulation via HDL to General-Purpose Language Translation
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Solution Overview
Problem
Current circuit design simulations face challenges in execution speed and accuracy, limiting the ability to test scenarios effectively and detect defects early in the design process.
Innovation Solution
The method involves generating a testbench and circuit design specifications in hardware description language, translating the circuit design into a cycle accurate model in a general-purpose programming language, and automatically generating an interface to simulate the circuit design's behavior at clock signal transitions, allowing for faster and more accurate simulation by comparing results between the original and translated models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation is performed using traditional hardware description language models, then accuracy in predicting actual hardware behavior is improved, but execution speed deteriorates
Solution Approach 1:
The patent segments the simulation process into two distinct parts: (1) a traditional HDL-based simulation for high accuracy verification, and (2) a translated general-purpose programming language simulation for fast execution. This segmentation allows each part to serve its optimal purpose without compromising the other, resolving the contradiction between accuracy and speed.
Solution Approach 2:
The patent creates a copy of the circuit design specification, translating it from hardware description language into general-purpose programming language. This copy enables fast simulation execution while the original HDL specification maintains accuracy for verification purposes, effectively resolving the speed-accuracy tradeoff.
2Reliability
If more simulation scenarios are attempted to detect defects, then defect detection capability is improved, but the time required for simulation increases
Solution Approach 1:
The patent implements periodic action by using the fast translated simulation to rapidly execute multiple test scenarios in cycles, enabling extensive defect detection coverage. The quick execution time allows numerous scenarios to be tested systematically, improving reliability without proportionally increasing time investment.
3Measurement precision
If traditional HDL simulation is used to ensure accurate prediction of circuit behavior, then measurement precision is improved, but productivity deteriorates due to long wait times
Solution Approach 1:
The patent introduces an intermediary translation layer that converts HDL specifications into general-purpose programming language. This intermediary enables fast simulation execution for routine verification tasks, while the original HDL specification remains available for high-accuracy verification when needed, thus improving productivity without sacrificing measurement precision.
Data Source
AI summary
Various approaches for simulating a circuit design are disclosed. In one approach, a first specification of a testbench and a second specification of the circuit design are generated in a hardware description language. The circuit design is synchronous to at least one clock signal. The second specification of the circuit design is automatically translated into a third specification in a general-purpose programming language, and the third specification specifies the behavior of the circuit design at transitions of the at least one clock signal. A fourth specification of an interface between the first specification of the testbench and the third specification of the circuit design is automatically generated. A first behavior of the circuit design is simulated using the first and third specifications linked by the fourth specification and the stimuli from the test bench.