Circuit Simulation Parasitic Modeling Layout Analysis
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Solution Overview
Problem
Conventional pre-layout simulation of integrated circuits fails to accurately consider the impact of parasitic effects from metal wiring, leading to significant differences between simulation results and actual chip measurements, thereby reducing simulation accuracy.
Innovation Solution
A method that determines the top-layer structure and minimum circuit cell layer of a circuit schematic, adjusts the area and relative distribution of target circuit cells in the layout, and adds a parasitic effect circuit to simulate the parasitic impact, generating a target circuit structure for accurate pre-layout simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pre-layout simulation is performed without considering metal wiring parasitic elements, then the simulation process is simple and fast, but the simulation accuracy is low and differs significantly from actual chip measurements
Solution Approach 1:
The simulation model is segmented into modular components: extracting circuit cells from the schematic, identifying their spatial relationships in the layout, and separately calculating parasitic effects for each cell based on its position and surrounding structures. This modular approach allows accurate parasitic modeling without requiring a completely complex full-wave simulation of the entire circuit.
Solution Approach 2:
The method performs preliminary extraction of circuit cells and their spatial relationships from the layout before simulation. By pre-identifying the top-layer structure, minimum circuit cell layer, and relative distribution locations, the system prepares all necessary geometric information in advance, enabling accurate parasitic calculation to be integrated smoothly into the pre-layout simulation flow without major structural changes.
2Measurement precision
If parasitic effect representation models are added to improve accuracy, then simulation results better match actual measurements, but the complexity of the simulation model increases
Solution Approach 1:
The patent applies local quality by calculating parasitic effects specifically for circuit cells based on their individual spatial characteristics and surrounding structures. Each circuit cell's parasitic parameters are determined by its specific location, area, and neighboring elements in the layout, rather than applying a uniform complex model to the entire circuit. This localized approach maintains accuracy while controlling overall complexity.
Solution Approach 2:
The method introduces an intermediary process that extracts geometric information from the layout (cell areas, relative distribution locations, top-layer structure) and uses this information to calculate parasitic effects. This intermediary geometric representation serves as a bridge between the simple schematic and the complex physical reality, enabling accurate parasitic modeling without directly importing full layout complexity into the simulation.
3Measurement precision
If the impact of subsequent metal wiring parasitic elements is considered in pre-layout simulation, then simulation accuracy improves, but the simulation process becomes more complex
Solution Approach 1:
The patent incorporates parasitic effects by adding a new dimension of spatial analysis to the pre-layout simulation. By extracting and analyzing the minimum circuit cell layer and relative distribution locations from the layout, the method brings in geometric spatial information as an additional dimension that enables parasitic calculation without requiring full three-dimensional electromagnetic simulation complexity.
Data Source
AI summary
Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.