Automated Regular Expression Generation for Circuit Simulation
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Solution Overview
Problem
Manual provision of regular expressions for gate-level simulation/verification of electronic circuits is inefficient, leading to incomplete design scanning, multiple iterations, large memory footprints, and prolonged simulation times, causing frustration for verification engineers.
Innovation Solution
A method that automatically generates a list of regular expressions based on parsing the electronic circuit design at a higher level, pruning connectivity descriptors, and optimizing simulation at a lower level, reducing redundant elements and combinatorial logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual provision of regular expressions is used for gate-level simulation, then verification coverage can be achieved, but simulation time increases and productivity decreases
Solution Approach 1:
The system performs preliminary analysis at the RTL level to automatically generate regular expressions before gate-level simulation. This preliminary action identifies all elements requiring verification and creates the regex patterns in advance, eliminating the need for manual provision during simulation and significantly reducing simulation time while maintaining complete verification coverage.
Solution Approach 2:
The verification system becomes self-service by automatically generating its own regular expressions from the RTL design without human intervention. The system parses the RTL code, identifies verification targets, and autonomously creates the regex patterns needed for gate-level simulation, freeing engineers from manual regex provision and accelerating the simulation process.
2Reliability
If manual regular expression provision is used, then verification can be performed, but multiple iterations are required and time is lost
Solution Approach 1:
The system performs complete verification planning at the RTL level before simulation, automatically generating all necessary regular expressions in one pass. This preliminary action ensures that all verification scenarios are covered from the start, eliminating the need for iterative adjustments and reducing the number of simulation passes required.
Solution Approach 2:
The system uses feedback from RTL-level analysis to automatically refine and complete the regular expression set before gate-level simulation begins. By analyzing the RTL design structure and verification requirements, the system adjusts the regex patterns to ensure complete coverage, preventing iteration failures and reducing re-simulation needs.
3Reliability
If complete design scanning is attempted manually, then comprehensive verification is possible, but memory footprint increases
Solution Approach 1:
The verification process is segmented into two levels: RTL-level analysis for comprehensive design scanning and gate-level simulation for detailed verification. The RTL-level segmentation allows complete design coverage to be analyzed and regular expressions to be generated without loading the entire gate-level design into memory, thus maintaining comprehensive coverage while reducing memory footprint during simulation.
Solution Approach 2:
The system transitions from a single-level approach to a two-dimensional verification strategy, moving from gate-level to RTL-level for the analysis phase. This dimensional shift allows comprehensive design scanning to occur at the higher RTL abstraction level with minimal memory requirements, while gate-level simulation uses only the generated regular expressions, avoiding the need to hold the complete gate-level design in memory.
4Reliability
If manual verification processes are used, then verification can be completed, but device complexity and operation difficulty increase
Solution Approach 1:
The verification system performs self-service by automatically generating regular expressions from RTL design analysis without requiring manual configuration. The system autonomously parses the RTL code, identifies verification targets, and creates appropriate regex patterns, eliminating complex manual processes while maintaining verification accuracy through systematic RTL-level analysis.
Solution Approach 2:
The RTL-level analysis engine serves multiple functions: it parses the design, identifies verification targets, generates regular expressions, and validates coverage. This multi-functional approach consolidates what would otherwise require separate manual processes into a single automated system, reducing operational complexity while maintaining comprehensive verification capability.
Data Source
AI summary
A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit at a first level higher than a second level at which design verification and/or design simulation of the electronic circuit is to be conducted, and representing instances of elements of the electronic circuit in a data structure. The method also includes parsing, at the first level, the design to automatically generate a list of regular expressions related to text-matching strings with the elements of the electronic circuit based on removing undesired instances related to the elements from the data structure, and pruning, at the second level, connectivity descriptors of the electronic circuit based on the automatically generated list of regular expressions. Further, the method includes optimizing the design verification and/or the design simulation at the second level based on the pruned connectivity descriptors thereof.