Circuit Simulator Checkpointing via Process Forking
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Solution Overview
Problem
Digital IC designers face significant time-consuming re-simulation processes when debugging circuit designs, as existing methods require frequent disk accesses to save and restore checkpoint data, which slows down the simulation and re-simulation processes.
Innovation Solution
Implementing a method where the circuit simulator forks a checkpoint process to create suspended checkpoints, allowing for quick resumption of simulations without the need for disk access, by copying memory content and using a 'copy-on-write' technique to share memory until modifications occur, thereby reducing processing time for creating and initiating re-simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the simulator saves checkpoint data to hard disk during simulation, then the checkpoint can be preserved for later re-simulation, but the simulation process becomes slower due to frequent disk accesses
Solution Approach 1:
The patent creates a copy of the simulation process at checkpoint moments using process forking. Instead of writing checkpoint data to disk, the system forks a new process that inherits the parent process's memory space, effectively copying the simulation state into a suspended child process that can be resumed later without disk I/O operations.
Solution Approach 2:
The patent replaces the mechanical disk I/O system with an in-memory process management system. By using process forking and memory inheritance, the system eliminates the need for physical disk access to save and restore checkpoints, substituting the mechanical storage system with a memory-based process state management approach.
2Measurement precision
If the simulator re-simulates the entire circuit to debug internal signals, then detailed waveform data can be obtained, but the debugging process becomes very time-consuming
Solution Approach 1:
The patent segments the simulation process into independent checkpoint processes that can be individually managed. By forking the simulation process at checkpoints, the system creates discrete, suspendable process instances that can be resumed selectively, allowing detailed waveform collection only when and where needed rather than continuous full-circuit re-simulation.
Solution Approach 2:
The patent performs preliminary process forking at checkpoint moments during the original simulation. By creating suspended checkpoint processes in advance that inherit the simulation state at critical moments, the system prepares ready-to-resume process instances beforehand, eliminating the need for time-consuming full re-simulations when debugging issues.
3Loss of information
If the simulator writes waveform data to hard disk frequently, then complete simulation data is preserved, but RAM space is consumed and disk access time increases
Solution Approach 1:
The patent uses process forking to create copies of the simulation process state in memory rather than copying waveform data to disk. The child processes inherit the parent's memory space containing complete simulation data, preserving information完整性 while keeping all data in RAM accessible to the CPU without disk I/O delays.
Data Source
AI summary
A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.