Automated Circuit Specification Translation via NLP

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Solution Overview

Problem

The manual translation of natural language specifications into SystemVerilog Assertions for electronic circuit design verification is time-consuming and costly, accounting for up to 50% of hardware design costs due to the complexity of assertions and the need for manual effort.

Innovation Solution

A system and process that utilizes Machine Learning (ML) and Natural Language Processing (NLP) to automatically translate intellectual property block specifications from natural language to SystemVerilog Assertions by parsing sentences, extracting semantic concepts, and generating probabilistic shift-reduce schedules to produce syntactically correct and semantically accurate code.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual translation of natural language specifications to SystemVerilog Assertions is performed, then verification accuracy is improved, but productivity deteriorates and time consumption increases

Engineering Contradiction:

Improveverification accuracyVSAvoidtranslation speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the manual mechanical translation process with an automated natural language processing system. The system uses NLP models to parse natural language specifications, extract verification conditions, and generate SystemVerilog Assertions automatically, eliminating the need for manual translation while maintaining verification quality

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary NLP-based translation system between natural language specifications and SystemVerilog Assertions. This intermediary automatically transforms natural language into verification code, bridging the gap between human-readable specifications and machine-verifiable assertions without requiring manual intervention

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If manual translation of natural language specifications to SystemVerilog Assertions is performed, then assertion accuracy is improved, but cost increases

Engineering Contradiction:

Improveassertion accuracyVSAvoiddevelopment cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive manual translation services with an automated NLP system. By using machine learning models trained on verification language patterns, the system achieves high assertion accuracy while eliminating the labor costs associated with manual translation, reducing verification development costs significantly

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If automated translation using NLP is implemented, then productivity is improved, but translation accuracy may deteriorate

Engineering Contradiction:

Improvetranslation speedVSAvoidtranslation accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary actions by training NLP models on extensive datasets of natural language specifications and their corresponding SystemVerilog Assertions. This pre-training enables the automated system to understand verification language patterns, improving translation accuracy while maintaining high productivity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the automated translation system's outputs are evaluated and used to refine the NLP models. This continuous improvement process enhances translation accuracy over time while maintaining the productivity benefits of automation

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250068846A1Automated translation of design specifications of electronic circuits

Publication Date: 2025.02.27 SYNOPSYS INC

AI summary

Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.