Circuit Substrate Layout for Thin, Low-Resistance Die Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing resistance and enhancing heat dissipation while maintaining a compact form factor, particularly in the integration of semiconductor dies and redistribution circuits without the use of solder balls.
Innovation Solution
A circuit substrate with an integrated semiconductor die and a redistribution element that provides horizontal and vertical electrical connections, formed using a base substrate with thermally conductive materials and conductive blocks, allowing for a stack structure with reduced thickness and improved heat dissipation without solder balls, and further bonded to a printed circuit board for external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor packaging with solder balls is used, then electrical connections are established, but resistance is high and heat dissipation is poor
Solution Approach 1:
The patent changes the material parameters of the connection structure by replacing solder ball materials with copper pillar and mold compound materials, achieving lower resistance and improved thermal conductivity. The copper pillar provides excellent electrical conductivity while the mold compound with high thermal conductivity fills the space to enhance heat dissipation, fundamentally changing the physical parameters of the connection path.
Solution Approach 2:
The patent employs a composite structure consisting of copper pillars embedded in mold compound. The copper provides electrical conductivity and structural support, while the mold compound provides thermal management and mechanical protection. This composite material approach combines the advantages of different materials to simultaneously achieve low resistance and high heat dissipation capability.
2Productivity
If redistribution circuits are integrated at wafer level, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the redistribution circuit integration process into distinct stages: forming copper pillars on the wafer, applying mold compound to encapsulate and connect, and subsequent processing. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing process compared to traditional full wafer-level redistribution, making high-density integration more manufacturable.
3Reliability
If solder balls are used for connections, then electrical connections are established, but the package size increases
Solution Approach 1:
The patent extracts the spherical solder ball component from the connection structure and replaces it with cylindrical copper pillars. This geometric extraction reduces the vertical space required for connections, allowing for thinner package designs while maintaining reliable electrical connections. The copper pillars provide direct vertical pathways that minimize the distance signals and power must travel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a semiconductor package with reduced resistance and enhanced heat dissipation capabilities, enabling more efficient thermal management and compact design without the need for solder balls, thereby improving performance and reliability.
Implementation Method 1
formed using a base substrate with thermally conductive materials
Data Source
AI summary
A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure. The semiconductor die is located over the base substrate and laterally arranged next to the second redistribution circuit structure.