Circuit Substrate Multilayer Routing for Narrow-Frame Tiled Displays
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Solution Overview
Problem
Current driving elements in display electronic devices occupy significant frame space, hindering the development of narrow or frameless designs.
Innovation Solution
The gate and data driving circuits are centrally disposed on one side of the circuit substrate, connected via connection lines, allowing for tiling of multiple substrates to create a large display with narrow or borderless frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If driving circuits are disposed at both sides of the substrate, then the driving function is ensured, but the frame width becomes considerable and narrow frame design is hindered
Solution Approach 1:
The patent merges both the gate driving circuit and data driving circuit into a single peripheral area at one side of the substrate. This consolidation allows both driving functions to coexist in a compact arrangement, eliminating the need for separate driving circuits at both sides, thereby reducing frame width while maintaining complete driving functionality.
2Reliability
If driving circuits are disposed at both sides of the substrate, then the driving function is ensured, but transmittance of display area is reduced
Solution Approach 1:
By consolidating both gate and data driving circuits into one peripheral area, the patent removes driving circuit elements from the other side of the substrate. This creates an unobstructed path for light transmission through the display area, maximizing transmittance while the merged driving circuits maintain full driving capability.
3Illumination intensity
If driving circuits are concentrated at one side, then transmittance is improved and narrow frame is enabled, but circuit connection complexity increases
Solution Approach 1:
The patent utilizes multiple metal layers (first metal layer, second metal layer, third metal layer) to route connection lines in three-dimensional space. This layered approach allows complex connections between driving circuits and scan lines to be organized vertically, reducing lateral complexity and enabling compact single-side configuration while maintaining clear signal paths.
Data Source
AI summary
An embodiment of the disclosure provides a circuit substrate and a tiled electronic device. The circuit substrate includes a substrate and first to third metal layers. The first metal layer is disposed on the substrate and includes first and second connection lines, and first and second scan lines. The first and second connection lines are electrically connected to the first and second scan lines, respectively. The second scan line includes two separate line segments respectively located at opposite sides of the first connection line. The second metal layer is disposed on the substrate and includes a first data line. The first data line is overlapped with the first connection line. The third metal layer is disposed on the substrate and includes a bridge line. The bridge line is electrically connected to the line segments. The second metal layer is disposed between the first and third metal layers.