Circuit Substrate With Thickness-Enhancing Conductive Patterns
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high routing density and bump density to meet the demands of integrated multi-chip packages and multiple I/O terminals, which limits the efficiency of chip connections to electronic devices.
Innovation Solution
A circuit substrate design featuring conductive line patterns directly connected to through via plugs, with thickness enhancing conductive patterns on pads, allowing for increased bonding strength and density using the bump-on-trace (BOT) technology, where the conductive line patterns and through via plugs are formed of the same materials to enhance routing and bump density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional circuit boards with laminated conductive and dielectric layers are used, then basic electrical connection is achieved, but routing density and bump density are insufficient to meet multi-chip package requirements
Solution Approach 1:
The patent transitions from conventional planar routing to three-dimensional vertical routing by implementing through-via plugs that penetrate the substrate thickness direction. This allows signal transmission in the thickness dimension, enabling high-density routing without increasing the planar footprint, thereby resolving the contradiction between routing density and connection efficiency.
Solution Approach 2:
The patent employs nested conductive structures where thickness-enhancing conductive patterns are positioned on top of pads, which are connected to through-via plugs that extend through the substrate. This nested arrangement maximizes the use of vertical space, increasing both routing density and bump density while maintaining compact packaging.
2Quantity of substance
If routing density is increased to meet multi-chip package requirements, then connection capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the conductive structure into distinct segments: through-via plugs for vertical connection, pads for bonding interface, and thickness-enhancing conductive patterns for reinforcement. This segmentation allows each component to be optimized independently while achieving high routing density, thereby managing manufacturing complexity through modular design.
Solution Approach 2:
The patent applies thickness-enhancing conductive patterns selectively at specific locations (on top of pads) rather than uniformly across the entire substrate. This localized enhancement provides necessary structural reinforcement and electrical performance only where required, reducing overall manufacturing complexity while achieving high routing density at critical interfaces.
3Quantity of substance
If bump density is increased for higher I/O terminals, then packaging capacity improves, but bonding strength becomes insufficient
Solution Approach 1:
The patent creates a composite conductive structure combining through-via plugs, pads, and thickness-enhancing conductive patterns. This composite structure provides both the high bump density required for multi-I/O packaging and the enhanced bonding strength through multiple conductive layers and increased interface area, resolving the contradiction between density and strength.
Solution Approach 2:
The patent enhances bonding strength by extending the conductive structure in the thickness dimension through through-via plugs and thickness-enhancing patterns. This vertical extension increases the bonding interface area and provides mechanical reinforcement, enabling high bump density while maintaining adequate bonding strength.
Data Source
AI summary
A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.