Circuit Switched Memory Access for Multi-Core Data Transfer
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Solution Overview
Problem
Current computing device architectures using bus architectures for memory intercommunication become inefficient and wasteful as the number of cores and memory clients increases, leading to slowed data transfer and hardware resource wastage due to the need for wide, long buses that block other clients during data access.
Innovation Solution
Implementing circuit switching to connect shared memory banks with memory clients, allowing simultaneous access and reducing hardware requirements by establishing dedicated connections between memory banks and clients, thereby optimizing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bus architecture is used to connect memory banks and clients, then data transfer between memory and clients is enabled, but hardware resource usage increases and data transfer efficiency decreases due to blocking
Solution Approach 1:
The patent divides the shared memory resource into multiple independent memory banks, each capable of being accessed simultaneously by different clients. This segmentation allows parallel access patterns where Client 1 can access Memory Bank 1 while Client 2 accesses Memory Bank 2, eliminating the blocking effect inherent in bus architectures and improving overall data transfer efficiency without requiring additional hardware resources.
2Productivity
If wide data buses are used to increase bandwidth, then data transfer capacity increases, but physical hardware cost and complexity increase
Solution Approach 1:
The patent transitions from a one-dimensional bus architecture where all clients share a single communication path to a two-dimensional matrix architecture where clients and memory banks are arranged in rows and columns. This dimensional change enables multiple simultaneous access paths, effectively increasing bandwidth without requiring wider individual data buses, thus avoiding the associated hardware complexity and cost.
3Device complexity
If a single bus serves multiple clients, then hardware resource usage is minimized, but access time increases due to client blocking
Solution Approach 1:
The patent ensures continuous useful action by enabling multiple clients to access different memory banks simultaneously without blocking. While a bus architecture would force clients to wait in sequence, the banked memory architecture with circuit switching allows Client 1, Client 2, Client 3, etc. to all perform memory operations at the same time, eliminating idle waiting periods and reducing total access time while using comparable hardware resources.
4Productivity
If circuit switching is implemented to enable simultaneous access, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The patent implements self-service through self-routing logic where the address information itself controls the switching operation. The most significant bits of the memory address automatically configure the circuit switches to establish the correct connection path from the requesting client to the target memory bank, eliminating the need for external control logic or complex arbitration mechanisms. This reduces the overall device complexity while maintaining high memory access efficiency.
Data Source
AI summary
A computing device includes a transport switch comprising read and write switches that provide switched circuit interconnections between input and output ports for simultaneous data communication between a plurality of memory clients and a plurality of memory banks, such as between cores of a multi-core processor simultaneously accessing L1, L2, and L3 memory banks. Embodiments implement switching designs that are derived from existing switched network architectures. Other embodiments implement a novel circuit switch design based on 8×8 building blocks. The transport switch can be non-blocking, and can be self-routing. An additional switching layer can be included to provide port rearrangement for rearrangeable non-blocking switches. A transport compiler can be used to determine port-pair configurations of the switch. A disclosed method selects optimal switch architectures for specific applications. Embodiments support simultaneous, multicast transfers of data retrieved from a memory bank to a plurality of memory clients.