Circuit Synthesis Lookup Table for Timing Area Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing iterative trial-and-error approaches for circuit synthesis are inefficient and produce poor results for large circuit designs, especially when checking timing constraints across many process corners and modes.
Innovation Solution
The creation of a lookup table that associates output loads with optimal or near-optimal cell configurations, using a load-based or logical-effort-based lookup table, to optimize cells in a reverse-levelized cell ordering, concurrently optimizing timing, area, and power leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error approach is used to optimize circuit designs, then timing constraints can be checked across process corners and modes, but the synthesis process takes too long to complete
Solution Approach 1:
The patent pre-calculates and stores optimal cell sizing information in lookup tables before the actual synthesis process. During synthesis, the optimizer directly queries these pre-computed tables to retrieve optimal cell sizes, eliminating the need for iterative trial-and-error during the synthesis process itself. This preliminary preparation resolves the contradiction by making the optimization step extremely fast while maintaining timing constraint satisfaction.
Solution Approach 2:
The patent creates lookup tables that contain pre-computed optimal cell configurations for various loading conditions and process corners. Instead of performing iterative optimization during synthesis, the system copies pre-determined optimal solutions from these tables into the design, achieving both speed and reliability.
2Manufacturing precision
If iterative trial-and-error approach is used to optimize circuit designs, then cell sizes can be adjusted to meet timing constraints, but the optimization process produces poor quality results for large circuit designs
Solution Approach 1:
The patent performs comprehensive cell sizing optimization in advance and stores the results in lookup tables. During the actual synthesis process, these pre-optimized cell sizes are directly applied, ensuring high manufacturing precision without the computational overhead of iterative optimization during synthesis.
3Reliability
If comprehensive timing analysis is performed across many process corners and modes, then timing reliability is improved, but the computational time increases significantly
Solution Approach 1:
The patent pre-computes timing characteristics and optimal cell sizes for multiple process corners and modes, storing this comprehensive timing analysis data in lookup tables. During synthesis, the system simply queries these pre-analyzed tables, achieving timing reliability across all process corners without repeating the computationally expensive analysis during synthesis.
Solution Approach 2:
The patent copies pre-computed timing data and optimal cell configurations from lookup tables that were generated through comprehensive process corner analysis. This allows the synthesis process to benefit from thorough timing analysis without incurring the computational time penalty during actual synthesis.
Data Source
AI summary
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.