Circuit Synthesis Tracking for Logic Removal Root-Cause Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the synthesis of programmable logic integrated circuits, logic circuits are often removed due to issues like stuck inputs, lack of fanouts, or duplication, with conventional methods failing to effectively inform designers about the reasons for removal and their consequences, leading to difficulties in debugging and verification.
Innovation Solution
A system and method to track and report the removal of logic circuits, including their reasons and consequences, by creating a database that records and propagates related optimizations, allowing designers to trace back to root causes and visualize optimization sequences through user interfaces and RTL viewers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic circuits are removed during synthesis to optimize the circuit design, then the circuit complexity is reduced and synthesis efficiency is improved, but the ability to debug and verify the design is worsened due to lack of information about removal reasons and consequences
Solution Approach 1:
The system performs preliminary recording of logic circuit removal information during the synthesis process itself. As the synthesizer removes logic circuits, it simultaneously records the removal reasons, affected circuits, and optimization sequences in a database, making this information available before debugging is needed.
Solution Approach 2:
The system establishes feedback by providing debugging information back to the designer through queryable databases and visualizations. The synthesizer feeds back removal reasons, consequences, and optimization sequences to the design tool, enabling effective debugging and verification despite circuit optimizations.
2Difficulty of detecting and measuring
If comprehensive tracking of all logic circuit optimizations is implemented, then debugging capability is improved, but the system complexity and computational overhead increase
Solution Approach 1:
The system extracts only the essential debugging information from the synthesis process - specifically removal reasons, affected circuit relationships, and optimization sequences. This selective extraction provides adequate debugging capability without tracking every detail of the synthesis process, thereby limiting system complexity.
Solution Approach 2:
The system introduces an intermediary database and tracking module that sits between the synthesizer and the designer. This intermediary captures and organizes optimization information in a structured format, simplifying the interface between the complex synthesis process and the debugging needs of designers.
3Manufacturing precision
If detailed optimization information is recorded and propagated through the design hierarchy, then verification accuracy is improved, but the time required for synthesis and analysis increases
Solution Approach 1:
The system performs preliminary recording of optimization information during the synthesis process itself, capturing removal reasons, affected circuits, and relationships as they occur. This eliminates the need for separate analysis passes and provides accurate verification information without significant time penalty.
Solution Approach 2:
The system implements partial tracking by focusing only on logic circuit removals and their immediate consequences, rather than tracking all possible optimization types. This selective approach provides sufficient verification accuracy for debugging while limiting the time overhead to essential information only.
Data Source
AI summary
A method is provided for using an integrated circuit design tool to optimize a circuit design for an integrated circuit. Optimizations that affect first circuits in the circuit design and that are performed during synthesis of the circuit design for the integrated circuit are recorded in first records in a database. Second records are recorded in the database that indicate second circuits in the circuit design that fanin to or fanout from the first circuits and that are affected by the optimizations. A root cause of at least one of the optimizations is determined using the first and the second records in the database. A sequence of the optimizations affecting the first and the second circuits is determined using the first and the second records in the database.