Digital Circuit Test Memory for Real-Time Signal State Analysis
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Solution Overview
Problem
The complexity of testing and verifying performance of integrated circuits, particularly ASIC and SOC designs, leads to high costs and inefficiencies due to the need for extensive memory blocks and time-consuming analysis of signal states, with existing methods failing to provide efficient, customizable testing and analysis solutions.
Innovation Solution
A digital circuit testing and analysis module utilizing a high-density memory with one-bit wide words, where digital signal combinations are used as addresses to determine test and analysis status, allowing for efficient look-up processes and customizable testing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive memory blocks are used for testing and analysis, then analysis capabilities are improved, but chip area usage increases
Solution Approach 1:
The patent segments the extensive memory into multiple smaller memory blocks, each dedicated to specific test patterns or analysis functions. This allows the system to achieve comprehensive analysis capabilities while using less total chip area by organizing memory resources efficiently rather than using one large contiguous block.
Solution Approach 2:
The memory blocks are designed to serve multiple functions - they can be configured for different test patterns, analysis types, and can be selectively activated based on testing needs. This multi-functionality allows comprehensive analysis capabilities without requiring dedicated memory for each function, thus reducing overall chip area usage.
2Reliability
If more test patterns are used to test complex ASIC, then testing accuracy is improved, but memory block size increases
Solution Approach 1:
The patent implements dynamic memory allocation where memory blocks can be selectively activated and deactivated based on the specific test pattern being executed. This allows the system to support a large number of test patterns for high testing accuracy while keeping the active memory footprint small at any given time, as not all memory blocks need to be simultaneously accessible.
Solution Approach 2:
Test patterns are pre-organized and mapped to specific memory blocks before testing begins. This preliminary organization allows the system to load only the necessary memory blocks for each test sequence, reducing the amount of memory that needs to be physically present in the chip while still supporting comprehensive testing accuracy.
3Quantity of substance
If JTAG scanning registers are used for testing, then test pattern storage is improved, but chip area and cost increase
Solution Approach 1:
The patent merges the test pattern storage function with the analysis memory blocks, eliminating the need for separate JTAG scanning registers. The same memory infrastructure used for pattern storage during design simulation is utilized during physical testing, reducing chip area by consolidating functions rather than adding dedicated testing hardware.
Solution Approach 2:
The system uses its existing memory infrastructure to serve testing needs without requiring additional dedicated testing components. The memory blocks that are already present for design and simulation purposes are repurposed and configured to handle test pattern storage and analysis, allowing the system to be self-sufficient for testing without external add-ons.
Data Source
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Figure 3A~3B
AI summary
The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.