Circuit Timing Analysis Simplification via Critical Clock Elimination
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Solution Overview
Problem
The existing methods for static timing analysis in electronic circuits are inefficient due to the need for repeated analysis across multiple modes and corners, leading to high computational costs and long turn-around times, especially when merging individual modes into a single merged mode results in complex analysis with increased clocks and timing constraints.
Innovation Solution
A computer-implemented method that identifies critical clock pairs in a circuit's timing nodes, eliminates non-critical clocks and their associated timing exceptions, and simplifies the mode description for analysis, reducing the number of clocks and constraints in the merged mode to enhance the efficiency of timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple individual modes are merged into a single merged mode, then the total number of combinations of modes and corners is reduced, but the number of clocks and timing constraints in the merged mode increases
Solution Approach 1:
The patent extracts and eliminates non-critical clocks from the merged mode by identifying only the critical clock pairs that affect timing violations. This is achieved by analyzing timing paths and determining which clocks are critical for timing verification, then removing non-critical clocks and their associated constraints from the merged mode description, thereby reducing complexity while maintaining analysis accuracy.
2Loss of time
If the number of clocks and timing constraints in the merged mode is reduced, then the analysis time and resource requirements decrease, but the accuracy of timing verification may be compromised
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical clocks based on their specific timing paths and constraints. Instead of uniformly treating all clocks equally, the system identifies local characteristics of each clock (such as whether it appears in critical timing paths) and applies selective elimination only to non-critical clocks, thereby maintaining verification accuracy for critical timing paths while reducing overall analysis time.
Data Source
AI summary
A mode of a circuit design is simplified by eliminating clocks and corresponding timing exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding timing exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on a comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding timing exceptions. The modified mode is used for performing timing analysis.