Circuit Timing Graph Analysis for Emulation Bottleneck Identification

The patent segments the large volume of timing information into hierarchical groups organized by design hierarchy levels (top-level modules, sub-modules, logic elements). This segmentation allows users to view information at appropriate levels of detail without being overwhelmed by the complete raw data set, resolving the contradiction between providing precise timing information and managing information volume.

The patent introduces visual dimensionality through graphical displays that map timing paths spatially across the design hierarchy. Instead of presenting timing data as flat text, the system creates multi-dimensional visual representations showing relationships between modules, paths, and timing parameters simultaneously, allowing comprehensive analysis without increasing textual information volume.

The patent performs preliminary computational actions by automatically calculating timing parameters, identifying critical paths, and organizing data by design hierarchy before presentation. The system pre-processes the comprehensive timing data to highlight the most significant information, eliminating the need for users to manually analyze all raw timing measurements and reducing operational effort while maintaining data completeness.

The patent introduces an intermediary computational layer that acts as a mediator between the raw timing data and the user. This intermediary automatically performs analysis functions such as identifying timing violations, calculating path delays, and organizing results by design hierarchy, thereby preserving complete timing information while eliminating manual analysis requirements.

The patent creates a universal reporting format that serves multiple functions simultaneously: it presents simplified internal emulator representation for clarity while also maintaining and displaying connections to original design hierarchy and connectivity information. The system integrates both views in a unified graphical interface, allowing users to see both the simplified emulator structure and its mapping to the original design without choosing one over the other.

The patent implements a nested information structure where the simplified emulator representation is embedded within the broader context of the original design hierarchy. The graphical display nests multiple levels of information - from top-level design modules down to individual logic elements - allowing users to see both the simplified internal representation and its relationship to the complete original design structure simultaneously.