Circuit Timing Adjustment for Single Event Upset Mitigation
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Solution Overview
Problem
Existing electronic circuit design processes face challenges in mitigating single event upset (SEU) errors, which are random and can cause unwanted behavior, with current solutions like triple mode redundancy increasing design size and cost, or degrading operating speed.
Innovation Solution
The approach involves modifying circuit designs by performing static timing analysis to determine positive slack in paths, adding delays to selected paths, and iteratively synthesizing and adjusting slack values to ensure they are within a threshold of 0, thereby reducing the occurrence of SEU errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple mode redundancy (TMR) is used to mitigate SEU errors, then reliability is improved, but device complexity and design size increase
Solution Approach 1:
The invention changes the timing parameter of critical paths by adding delays to reduce positive slack. This modifies the temporal characteristics of signal propagation without replicating circuit logic, thereby improving SEU mitigation while avoiding the complexity increase associated with TMR redundancy
2Reliability
If signal sampling at three different times is implemented, then SEU error mitigation is improved, but operating speed degrades
Solution Approach 1:
Instead of sampling signals at multiple time points, the invention adds delay elements to critical paths to adjust the timing parameter. This single-time-point approach with modified timing characteristics achieves SEU mitigation without the speed degradation caused by multiple sampling operations
3Reliability
If delays are added to reduce positive slack, then SEU error occurrence is reduced, but timing overhead increases
Solution Approach 1:
The invention applies delay elements selectively only to critical paths that have positive slack, rather than uniformly to all paths. This partial application approach achieves the necessary timing adjustment for SEU mitigation while minimizing the overall timing overhead introduced by delay elements
Data Source
AI summary
Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.