Circuit Design Timing and Yield Optimization via Virtual Analysis
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Solution Overview
Problem
Current circuit design optimization techniques fail to simultaneously improve timing and yield effectively, as timing improvements often reduce capacitive couplings while yield improvements increase them, leading to competing objectives in circuit design.
Innovation Solution
A process that estimates a realistic target timing delay by adjusting wire spacings and converting single-cut vias to double-cut vias, using virtual timing and yield optimization techniques to balance capacitive coupling and redundancy, allowing for incremental adjustments to achieve optimal timing and yield through wire spreading and via insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wire spacings are adjusted to reduce capacitive coupling, then timing is improved, but yield deteriorates
Solution Approach 1:
The system performs preliminary virtual timing optimization to identify potential timing violations before final layout completion. By analyzing the design layout and predicting timing delays, the system proactively identifies areas where wire spacing adjustments may be needed, allowing yield optimization to compensate for these changes in advance rather than reacting after timing degradation occurs
Solution Approach 2:
The system implements a feedback mechanism where the predicted timing delay from virtual timing optimization is fed back into the yield optimization process. The yield optimization uses this timing information to adjust via insertion strategies, converting single-cut vias to double-cut vias in critical areas to compensate for timing degradation caused by wire spacing reductions
2Reliability
If single-cut vias are converted to double-cut vias to improve yield, then redundancy increases, but capacitive coupling increases and timing deteriorates
Solution Approach 1:
The system applies local quality by selectively converting only certain single-cut vias to double-cut vias based on their specific location and impact on timing. The virtual timing optimization identifies critical paths and areas where via conversions are most beneficial for yield without excessively degrading timing, allowing different regions of the circuit to have different via densities and types optimized for their specific requirements
Solution Approach 2:
The system performs partial via conversion rather than converting all single-cut vias to double-cut vias. The yield optimization process selectively applies via conversions only where needed to achieve the target yield, avoiding excessive conversions that would unnecessarily increase capacitive coupling and degrade timing on non-critical paths
3Speed
If timing optimization is performed independently without yield consideration, then timing improves beyond specified value, but yield optimization independently performed results in timing degradation
Solution Approach 1:
The system merges the timing optimization and yield optimization processes into a unified iterative workflow. The virtual timing optimization and yield optimization are performed in sequence, with each process using information from the other, allowing the design to simultaneously satisfy both timing and yield requirements rather than treating them as separate competing objectives
Solution Approach 2:
The system implements a dynamic optimization process where the design layout is iteratively adjusted through multiple passes of virtual timing optimization and yield optimization. The process adapts to changing conditions in each iteration, modifying wire spacings and via configurations dynamically to converge on a solution that balances both timing and yield requirements
Data Source
AI summary
Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.