Circuit Topology Recognition for Layout Rule Generation
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Solution Overview
Problem
Designing analog and mixed signal electronic circuits becomes increasingly challenging due to pervasive layout dependent effects as technology nodes shrink, requiring more iterations between front-end and back-end design phases to meet specifications, making it difficult to account for these effects during the front-end phase.
Innovation Solution
A topology library is created that includes descriptions of transistors, their parameters, and connectivity rules, allowing tools to recognize specific circuit topologies, generate layout rules, and simulate criteria to automatically produce physical design layouts that meet design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If technology nodes are shrunk to improve integration density, then more transistors can be packed in a smaller area, but layout dependent effects become more pervasive and difficult to account for in the front-end phase
Solution Approach 1:
The patent applies preliminary action by performing topology recognition and layout rule generation during the front-end phase before physical layout is created. The system proactively identifies circuit topologies and generates corresponding layout rules that account for layout dependent effects, allowing designers to address these effects before they manifest as problems in later back-end iterations.
Solution Approach 2:
The patent introduces an intermediary system that includes a topology library and layout rule generator. This intermediary layer translates circuit topologies into specific layout rules, serving as a mediator between the schematic design phase and physical layout phase. The intermediary captures layout dependent effect information and converts it into actionable design rules.
2Manufacturing precision
If designers perform more back-end iterations to meet design specifications, then layout dependent effects can be better accounted for, but design time is extended
Solution Approach 1:
The system performs layout rule generation and topology verification during the front-end phase, which preliminarily addresses layout dependent effects before the back-end phase begins. This preliminary action reduces the number of iterations needed in the back-end phase while maintaining design specification compliance.
Solution Approach 2:
The patent implements feedback mechanisms where layout rules generated from topology recognition are fed back into the design process. The system continuously verifies that layouts conform to generated rules and provides feedback for corrections, enabling faster iteration cycles by avoiding redundant checks.
3Adaptability or versatility
If manual layout generation is used, then designers have flexibility in meeting design specifications, but the process is time-consuming and error-prone
Solution Approach 1:
The system enables self-service by automatically generating layout rules and physical layouts based on input circuit topologies. The topology recognition system and layout rule generator work autonomously to produce designs that meet specifications without requiring extensive manual intervention, while still maintaining the adaptability needed for different circuit configurations.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting layout rules based on detected topology characteristics. The system modifies layout parameters such as spacing, orientation, and positioning based on the specific circuit topology identified, enabling automated generation that adapts to different design requirements while maintaining high productivity.
Data Source
AI summary
This application discloses tools to build a topology library including one or more topologies, each of which includes a description of multiple transistors, their parameters, and associated connectivity, and also includes rules or criteria to be utilized in downstream design flow processes. The tools can analyze a circuit design describing an electronic device to recognize a subset of transistors in the electronic device has a pre-defined circuit topology, and identify layout rules or simulation criteria for the transistors in the recognized circuit topology. The tools can utilize the layout rules to automatically generate a portion of a physical design layout corresponding to the recognized topology in the circuit design. The tools also can compare results from a simulation of the circuit design that correspond to the transistors in the recognized circuit topology to the simulation criteria to determine whether the transistors in the recognized circuit topology meet design specifications.