Circuit Structure Recognition via Transistor Signature Encoding

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Solution Overview

Problem

Current circuit design methods, relying on electronic design automation (EDA) and computer-aided design (CAD), face inefficiencies in recognizing circuit structures from component connection descriptions due to the time-consuming process of establishing structure hierarchy trees and recursively identifying circuit subblocks.

Innovation Solution

A circuit encoding method that generates transistor signatures based on electrical connections, divides the circuit into groups, and compares group signatures to quickly recognize circuit subblocks, improving efficiency and accuracy by using terminal values and type codes to represent transistors and their connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the structure hierarchy tree is established and circuit sub blocks are recognized in a recursive manner, then the circuit structure can be accurately recognized, but the recognition process takes considerable time

Engineering Contradiction:
Improvecircuit structure recognition accuracyVSAvoidcircuit structure recognition time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the circuit into multiple transistor groups based on electrical connections (drain-source connections) before performing detailed recognition. This segmentation allows parallel processing of different groups and avoids the need to traverse the entire circuit hierarchy recursively, significantly reducing recognition time while maintaining accuracy through subsequent detailed comparison of grouped transistors

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary encoding of each transistor into a signature based on its electrical connections and characteristics before the main recognition process. This preliminary action creates ready-to-compare representations that enable fast matching against reference circuit sub blocks, eliminating the need for time-consuming recursive analysis during the actual recognition phase

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the circuit is divided into transistor groups according to electrical connections, then the preliminary division and determination can be conducted quickly, but additional encoding steps are required

Engineering Contradiction:
Improvecircuit division speedVSAvoidencoding algorithm complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transforms transistor characteristics and electrical connection information into compact signature parameters that capture essential circuit topology. This parameter transformation enables fast comparison operations while the signature structure is designed to be computationally efficient, balancing the added encoding steps against the gains in division speed and recognition accuracy

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10657303B2Circuit encoding method and circuit structure recognition method
Publication Date: 2020.05.19 REALTEK SEMICON CORP
  • US10657303B2 patent drawing
  • US10657303B2 patent drawing
  • US10657303B2 patent drawing

AI summary

This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.