Electronic Circuit Verification Optimization via Segmented BIST
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Solution Overview
Problem
The existing methods for verifying electronic circuits, such as Very-Large-Scale-Integration (VLSI) circuits, face challenges due to manufacturing defects caused by dense packing and complex designs, leading to lengthy runtime in Built-In Self-Test (BIST) simulations as they need to cover the entire address space of each element, and current techniques to reduce simulation time are either cumbersome or result in late bug detection.
Innovation Solution
A method that involves extracting a set of optimized instructions for a test algorithm to cover a maximum portion of logic functionalities in the electronic circuit design, executing only the relevant instructions to reduce verification time, using a combination of 'reduced MBIST test' and 'central controller test' to achieve 100% verification coverage while minimizing runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire address space of each element is covered for all BIST algorithms, then complete verification coverage is achieved, but the verification runtime becomes excessively long
Solution Approach 1:
The patent segments the verification process by dividing the complete BIST algorithm into multiple test cases, each targeting specific portions of the address space or specific fault types. This allows the verification to be broken down into manageable segments that can be executed selectively, achieving complete coverage through systematic segmentation rather than monolithic execution.
Solution Approach 2:
The patent applies partial action by selecting and executing only the necessary portions of the BIST algorithm rather than the complete algorithm. By analyzing the electronic circuit design, the system identifies and executes only those test cases needed to verify specific functionalities or detect specific fault types, avoiding redundant verification of already-validated portions.
2Reliability
If all BIST algorithms are executed to detect different types of structural faults, then comprehensive fault detection is achieved, but the simulation runtime increases significantly
Solution Approach 1:
The patent performs preliminary analysis of the electronic circuit design before execution to identify which BIST algorithms and test cases are most critical for detecting potential faults in that specific design. This preliminary characterization allows the system to prioritize and execute the most impactful verification cases first, improving simulation speed while maintaining comprehensive fault detection capability.
Solution Approach 2:
The patent implements dynamic verification by adjusting the verification strategy based on the specific characteristics of the electronic circuit design being verified. The system dynamically selects which BIST algorithms to execute based on the circuit's architectural features, data types, and potential vulnerability profiles, rather than using a static one-size-fits-all approach.
3Reliability
If the verification process covers all logic functionalities, then complete verification is achieved, but the verification time cannot be reduced
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor the verification progress and adjust the test case selection accordingly. By analyzing the results of executed test cases and the structural characteristics of the circuit, the system can identify patterns and optimize the verification sequence, potentially reducing verification duration while maintaining completeness through intelligent feedback-driven adaptation.
Data Source
AI summary
A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.