Circular Array Substrate for Wearable Displays
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Solution Overview
Problem
Conventional wearable smart watch technologies lack pixel structures designed for circular displays, limiting their design flexibility and functionality.
Innovation Solution
An array substrate with a circular or oval base substrate, featuring signal lines, thin film transistors, and pixel electrodes arranged in a concentric and radiating pattern, allowing for efficient display on circular or oval surfaces, with connection wires in a non-display region to facilitate frameless design and improved aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional rectangular pixel structures are used in wearable displays, then manufacturing processes are simple and standardized, but the display shape is limited to rectangular forms and design flexibility is reduced
Solution Approach 1:
The patent applies curvature by transforming the conventional rectangular pixel structure into a circular configuration. The data lines are designed as concentric circular arcs, gate lines as radial straight lines, and pixel electrodes as circular shapes, enabling the display to achieve circular or oval shapes while maintaining systematic arrangement and manufacturability
Solution Approach 2:
The patent introduces asymmetry in the layout arrangement by positioning the non-display region and connection wires at specific locations (e.g., one side of the circular display), allowing optimization of the aperture ratio and signal line routing while maintaining the overall circular symmetry of the pixel structure
2Area of stationary object
If signal lines are arranged in straight linear patterns, then manufacturing and routing are simplified, but the aperture ratio is reduced due to larger non-display regions required for connection
Solution Approach 1:
The data lines are designed as concentric circular arcs that follow the curvature of the circular display, allowing connection wires to be routed along the circumference in the non-display region. This curved arrangement reduces the area occupied by non-display regions compared to straight linear routing, thereby increasing the aperture ratio while maintaining systematic manufacturing processes
Solution Approach 2:
The patent utilizes the radial dimension by arranging gate lines as straight lines extending from the center to the periphery, perpendicular to the concentric circular data lines. This two-dimensional orthogonal arrangement (radial and circumferential directions) optimizes space utilization and increases the effective display area
3Area of stationary object
If connection wires are placed within the display region, then routing is simplified, but the display area is reduced and frameless design is compromised
Solution Approach 1:
The patent clearly segments the substrate into display region and non-display region. Connection wires are routed exclusively in the non-display region along the circular periphery, while pixel structures are confined to the display region. This spatial segmentation allows frameless design with maximum display area while providing dedicated space for connection routing
Solution Approach 2:
Connection wires are arranged along the circular circumference in the non-display region, following the curved geometry of the circular display. This curved peripheral routing eliminates the need for straight linear connection paths that would intrude into the display area, enabling frameless design while maintaining organized wire arrangement
Data Source
AI summary
The present disclosure discloses that an array substrate, including a base substrate having a circular or oval horizontal section, wherein the base substrate comprises a display region and a non-display region, wherein a plurality of first signal lines, a plurality of second signal lines crossing the plurality of first signal lines, a plurality of thin film transistors and a plurality of pixel electrodes are arranged in the display region, and the plurality of thin film transistors and the plurality of pixel electrodes are arranged in a plurality of pixel regions defined by the plurality of first signal lines and the plurality of second signal lines, wherein a connection wire connected to the plurality of first signal lines and the plurality of second signal lines is arranged in the non-display region.