Circular Buffer Clock Domain Crossing Circuit
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Solution Overview
Problem
Existing methods for asynchronous clock domain crossing, such as combining signals or using handshake mechanisms, face challenges with latency and cost when dealing with multiple clock domains of different frequencies, and FIFOs are expensive and consume significant chip area.
Innovation Solution
A clock domain crossing circuit using a circular buffer of D-type flip flops to generate enable signals for data transfer between clock domains, ensuring proper synchronization and metastability protection with minimal latency and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO memory is used for clock domain crossing, then reliability of data transfer is improved, but device cost and chip area increase
Solution Approach 1:
The patent divides the clock domain crossing function into two separate circuits: a first circuit in the first clock domain that generates control signals, and a second circuit in the second clock domain that receives and processes these signals. This segmentation eliminates the need for a shared FIFO memory structure, reducing chip area while maintaining reliable data transfer between asynchronous clock domains.
2Reliability
If a handshake mechanism is used for clock domain crossing, then synchronization reliability is improved, but latency increases
Solution Approach 1:
The patent uses preliminary action by pre-generating control signals in the first clock domain that encode both data and synchronization information. These control signals are prepared in advance and then directly transferred to the second clock domain, eliminating the need for iterative handshake protocols and reducing latency while maintaining synchronization reliability.
3Device complexity
If signal combination is used for clock domain crossing, then device complexity is reduced, but adaptability to different clock frequencies deteriorates
Solution Approach 1:
The patent employs parameter changes by designing control signals that can be dynamically adjusted to accommodate different clock frequencies and domains. The first and second circuits are configured to work with any asynchronous clock frequencies, making the solution adaptable and versatile without requiring complex reconfiguration mechanisms.
Data Source
AI summary
A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may be used to pass data between the two clock domains. In one embodiment, a set of storage devices is connected in a circular buffer arrangement. A first subset of the storage devices is clocked by a signal from a first clock domain and a second subset of the flip flops is clocked by a signal taken from a second clock domain. Respective output circuits generate enable signals to be used for transferring data between domains. In some implementations, a pulse is stored and registered by at least two of the storage devices in the first domain before being passed to the devices in the second domain. In other embodiments, the output circuits may include a pair of D flip flops, each clocked by a respective one of the first or second domain signals. In specific arrangements, an output flip flop takes its data input from a logical AND of signals output from a flip flop within its associated domain, to ensure that the enable signal is asserted for only a single output clock cycle, and/or a second flip flop uses a logical AND of its input and inverted output states to avoid metastable conditions.