Circular Command Queue Architecture to Prevent VM Page Faults

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Solution Overview

Problem

Traditional methods struggle with page faults during descriptor submission and completion address write operations in virtualized environments, leading to performance slowdowns and increased complexity, especially in memory overcommitment scenarios.

Innovation Solution

Implement a circular queue architecture with constrained descriptor and completion address ranges, using Guest Physical Addresses to allocate memory twice the standard size, with the VMM pinning these ranges to prevent page faults.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional descriptor queue methods are used in virtualized environments, then memory allocation flexibility is maintained, but page faults occur during descriptor fetch and completion status write operations causing performance slowdowns

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidcommunication reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent pre-allocates a completion address range in the host address space before descriptor submission. The VMM pins this pre-allocated range to prevent page faults during completion status writes. This preliminary allocation and pinning action eliminates the need for page fault handling during runtime, ensuring reliable and efficient bi-directional communication between guest software and hardware.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If memory overcommitment is implemented in virtualized environments, then memory utilization efficiency is improved, but page fault frequency increases leading to system instability

Engineering Contradiction:

Improvememory allocation flexibilityVSAvoidpage fault handling complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the host address space into distinct regions: a pinned completion address range and an unpinned general memory region. The VMM pins only the completion address range while allowing the rest of memory to be overcommitted. This segmentation enables memory overcommitment to proceed while isolating the critical completion write operations from page fault risks, reducing handling complexity.

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If descriptor queues are allocated with standard memory sizing, then memory utilization is optimized, but page faults occur during completion address write operations

Engineering Contradiction:

Improvememory allocation efficiencyVSAvoiddescriptor submission reliability

Core Design Contradiction:

Quantity of substanceVSEase of operation

Solution Approach 1:

The patent extends the traditional one-dimensional descriptor queue structure by adding a second dimension: the completion address range. Instead of merely allocating memory for descriptors, the system allocates and pins a separate completion address space. This dimensional extension ensures that completion writes have a guaranteed valid target address, eliminating page faults while maintaining efficient memory utilization for the descriptor portion.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260017084A1Efficient command queue architecture for faultless bi-directional communication

Publication Date: 2026.01.15 INTEL CORP

AI summary

This disclosure describes systems, methods, and devices related to enhanced bi-directional communication. A device may receive a descriptor queue base address and queue size from a virtual machine monitor. The device may allocate a memory region twice the size of a standard descriptor queue. The device may pin memory pages for both a descriptor region and a completion address region. The device may validate descriptor submissions based on a predefined completion address range.