Circular Decompressor for High Encoding Efficiency
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Solution Overview
Problem
Conventional sequential linear decompressors in the semiconductor industry face limitations in encoding efficiency, flexibility, and computational complexity during automatic test pattern generation, as they struggle to fully utilize the degree of freedom in the encoding process and handle encoding conflicts effectively.
Innovation Solution
The development of circular decompressors that utilize multiple circular shift registers and dynamic reseeding mechanisms to generate care bits, allowing for high encoding efficiency, flexible variable reception, and efficient encoding processes that can be directly incorporated into the ATPG implication process, while preventing encoding conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional sequential linear decompressors are used, then the device structure is simple, but the encoding efficiency is low and computational complexity is high
Solution Approach 1:
The decompressor is segmented into multiple independent circular shift registers (first, second, third, and fourth registers) that operate in parallel. Each register handles a portion of the test data bits, allowing simultaneous generation of multiple care bits. This segmentation enables the system to process more care bits per clock cycle while maintaining relatively simple individual register structures, thus resolving the contradiction between device complexity and encoding efficiency.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by introducing multiple circular shift registers that operate simultaneously. This dimensional change from time-sequential to space-parallel architecture allows the decompressor to generate multiple care bits in one clock cycle rather than sequentially, significantly improving encoding efficiency without proportionally increasing overall system complexity.
2Device complexity
If conventional sequential linear decompressors are used, then the device structure is simple, but the flexibility in variable reception is limited
Solution Approach 1:
The decompressor employs dynamic reseeding mechanisms where the circular shift registers can be selectively reseeded with new test data bits at different clock cycles. This dynamic operation allows the system to adaptively receive variables (test data bits) at different times and positions, providing flexibility in variable reception while maintaining a relatively simple fixed structure of the registers themselves.
Solution Approach 2:
Each circular shift register serves multiple functions: it can generate care bits, be selectively reseeded with new data, and operate in different modes (circular shifting vs. loading). This multi-functionality allows the decompressor to handle various test patterns and variable reception requirements using the same basic structural elements, enhancing flexibility without proportionally increasing device complexity.
3Ease of operation
If conventional sequential linear decompressors are used, then the encoding process is straightforward, but computational complexity during ATPG is high
Solution Approach 1:
The circular shift registers automatically generate care bits through their inherent circular shifting operation without requiring complex external control logic. Each register self-generates its output sequence by continuously circulating its contents, which simplifies the encoding process. The registers service themselves by maintaining their own state and generating outputs based on their internal structure, reducing the computational burden on external ATPG systems.
4Quantity of substance
If conventional sequential linear decompressors are used, then the hardware resources are minimal, but test data compression ratio is low
Solution Approach 1:
The patent combines multiple circular shift registers into a single decompressor unit that works together to generate care bits. By merging the outputs of multiple registers through logical operations (XOR gates), the system achieves a higher compression ratio than individual registers could provide alone. This merging allows the decompressor to process more test data bits simultaneously while using only minimal additional hardware resources compared to a single register.
Data Source
AI summary
Methods and apparatuses for generating compressed test data for use by a tester, decompressing the test data during test, and routing the decompressed test data into a set of scan chains within a circuit under test are described.