Circular DMA Buffer Reuse for Coherent High-Speed Data Transfer
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Solution Overview
Problem
Traditional DMA methods in high-speed interfaces like PCIe, USB, and Ethernet suffer from inefficiencies in data buffering, leading to increased power consumption and cache coherency issues, affecting transceiver performance and speed.
Innovation Solution
Implement a method involving coherent DMA mapping and a two-dimensional array of software descriptors to manage buffer units, using idle and scheduling indexes to optimize DMA access, reducing cache maintenance and improving data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional streaming DMA mapping is used for data buffering, then data transfer can be implemented, but each receiving and sending operation involves request and release of data buffer memory, affecting receiving and sending speed and increasing power consumption
Solution Approach 1:
The system pre-allocates n data buffer units from memory during initialization and creates a circular buffer structure. This preliminary action eliminates the need for repeated memory allocation and release operations during data transfer, as buffers are reused in a circular manner. The buffer management is set up in advance with software descriptors organized in a two-dimensional array, allowing efficient buffer selection without dynamic memory management overhead.
2Productivity
If traditional streaming DMA mapping is used for data buffering, then data transfer can be implemented, but it increases the power consumption of the hardware
Solution Approach 1:
The circular buffer structure enables continuous data transfer operations without interrupting buffer management. Once the circular buffer is established, the system can continuously perform data transfers by simply advancing the read and write pointers through the buffer array, eliminating repeated memory allocation/deallocation cycles that consume power. The coherent DMA mapping ensures continuous memory access patterns.
3Productivity
If traditional DMA mapping is used, then data transfer is possible, but cache coherency issues arise requiring API invocation to refresh or invalidate cache, making cache maintenance time-consuming and affecting transceiver performance
Solution Approach 1:
The system changes the memory mapping parameters by using coherent DMA mapping instead of traditional streaming mapping. This parameter change in the DMA configuration enables automatic cache coherency maintenance through hardware mechanisms, eliminating the need for software API calls to refresh or invalidate cache. The coherent mapping ensures that memory accesses by both CPU and DMA are automatically synchronized.
4Productivity
If traditional DMA mapping is used, then data transfer is possible, but it increases the power consumption of the hardware
Solution Approach 1:
The invention extracts the cache maintenance operations from the data transfer process by using coherent DMA mapping. The cache coherency management is taken out of the software domain (no API calls needed) and handled automatically by the hardware memory management unit (MMU) through coherent mapping, thereby eliminating the power consumption associated with frequent cache refresh and invalidate operations.
Data Source
AI summary
An improved data access method for direct memory access (DMA), comprising: allocating m DMA hardware descriptors, and n data buffer units from a data buffer to the controller; constructing software descriptors of the buffer into a two-dimensional array with each row directing to one buffer unit, wherein the value of a first subscript of each array item ranges between 0 and n−1, and the value of a second subscript ranges between 0 and 1; respectively storing a virtual and physical address of the same buffer unit in a column of the two-dimensional array of the corresponding software descriptor; creating an index to establish a directional relationship between the buffer units and the software descriptors, the index comprising an idle index and a scheduling index; and implementing the hardware and software descriptors access by the CPU and DMA to a memory in a data transfer process of the high-speed interface.