Circular TDC with Phase Interpolation for Finer Timing Resolution
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Solution Overview
Problem
Circular time-to-digital converters face limitations in achieving high timing resolution due to the delay of each delay cell, which restricts their ability to detect small timing differences effectively.
Innovation Solution
A circular delay chain and phase interpolator are used in conjunction with a time-to-digital (TDC) core to generate multi-phase clocks, allowing for improved timing resolution by propagating and interpolating clocks to determine the time difference between input signals, thereby enhancing detection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a circular delay chain is used to reduce the number of delay cells and increase detection range, then the detection range is improved, but the timing resolution is limited by the delay of each delay cell
Solution Approach 1:
The delay chain is divided into multiple segments or taps, where each tap provides a delayed version of the input signal. By segmenting the delay chain and using multiple taps simultaneously, the system achieves both extended detection range and improved timing resolution without requiring an excessive number of delay cells.
Solution Approach 2:
The patent transitions from a one-dimensional linear delay chain to a two-dimensional circular delay structure. This circular configuration allows the delay chain to wrap around, effectively doubling the detection range while maintaining compact implementation. The circular topology enables the system to measure timing differences beyond what a linear chain of the same length could achieve.
2Measurement precision
If more delay cells are added to improve timing resolution, then the timing resolution is improved, but the detection range is reduced
Solution Approach 1:
Each delay cell in the circular delay chain serves multiple functions: it provides delay for detection range extension while simultaneously contributing to timing resolution through its tapped output. The same physical delay cell structure fulfills both objectives, eliminating the need to choose between range and resolution.
Solution Approach 2:
The circular delay chain enables continuous measurement across the full detection range by wrapping the delay path back on itself. This continuous circular structure ensures that timing resolution is maintained throughout the entire detection range, rather than degrading at the edges of the measurement window.
3Device complexity
If the number of delay cells is reduced to simplify the device, then the device complexity is reduced, but the timing resolution deteriorates
Solution Approach 1:
The system uses dynamic signal processing techniques, including phase interpolation and digital signal manipulation, to achieve high timing resolution from a fixed, compact delay chain structure. By dynamically processing the signals from the limited number of delay cells, the system extracts fine timing information without requiring additional physical delay elements.
Solution Approach 2:
The patent introduces intermediate processing stages, such as phase interpolators and digital signal processors, that act as mediators between the physical delay cells and the final timing measurement. These intermediaries extract and amplify timing information from the limited delay cell outputs, achieving high resolution without increasing the number of physical delay cells.
Data Source
AI summary
A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.