CMOS Image Sensor Column Routing Matrix for Down-Sampling Readout
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Solution Overview
Problem
Current CMOS image sensors (CIS) designs are limited in their ability to utilize all column analog-to-digital converters (ADCs) during down-sampling read operations, such as (V:½, H:½) and (V:⅓, H:⅓) down-sampling, resulting in inefficient use of ADC resources and slower readout speeds due to the skipping of columns and rows.
Innovation Solution
The implementation of a column routing matrix that routes signals from all column-out signal paths to all column ADCs, allowing for the utilization of all ADCs during various read operations, including (V:½, H:½) and (V:⅓, H:⅓) down-sampling, by configuring control signals to enable simultaneous reading of multiple rows or columns, thereby optimizing ADC usage and readout speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If down-sampling read operation is performed by skipping columns and rows, then readout speed is improved, but ADC resource utilization deteriorates
Solution Approach 1:
The patent implements dynamic routing that adapts the signal path based on the down-sampling pattern. The column routing matrix dynamically reconfigures which columns are routed to which ADCs, allowing the system to maintain full ADC utilization while performing down-sampling operations. This dynamic adaptation resolves the contradiction by making the routing flexible rather than fixed.
Solution Approach 2:
The patent introduces a column routing matrix as an intermediary component between the pixel array and the ADCs. This intermediary reconfigures the signal paths to ensure that during down-sampling operations, all ADCs remain actively utilized by redistributing the reduced set of active columns across the full set of ADCs, thereby maintaining resource utilization while achieving faster readout.
2Productivity
If all column ADCs are utilized during down-sampling, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the column routing into multiple independently controllable paths through the column routing matrix. By dividing the routing function into separate controllable segments, the system can efficiently manage signal distribution to maximize ADC utilization during down-sampling operations, achieving high productivity through organized modular routing.
Solution Approach 2:
The column routing matrix is designed as a universal routing structure that can handle multiple readout modes (full-frame, down-sampling at various ratios) through a single unified architecture. This multi-functional design allows the same hardware infrastructure to support different operational modes without requiring separate dedicated paths, thereby improving productivity while controlling complexity through resource sharing.
3Manufacturing precision
If conventional column parallel ADC architecture is used during down-sampling, then manufacturing precision is maintained, but productivity deteriorates
Solution Approach 1:
The patent applies dynamic routing control to the conventional column parallel ADC architecture, enabling the system to adapt its signal paths based on the specific down-sampling operation being performed. This dynamic capability allows the standardized ADC architecture to achieve higher productivity by fully utilizing all ADCs during down-sampling, rather than leaving them idle as in conventional fixed routing designs.
Data Source
AI summary
A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.