CMOS Image Sensor Package Fan-Out Structure

The patent transitions from lateral wire bonding to vertical through-substrate vias (TSVs) for electrical connection. By routing signals through the substrate thickness dimension rather than along the surface, the invention achieves shorter signal paths, higher bandwidth, and lower power consumption while maintaining the ability to accommodate size mismatch between CIS and DRAM dies through the fan-out structure.

The patent implements a stacked package architecture where the CIS die, fan-out structure, and DRAM die are vertically nested one on top of another. This three-dimensional stacking approach allows the package to accommodate size mismatches between components while minimizing the overall footprint and volume, creating a compact integrated assembly rather than a spread-out layout.

The patent replaces the mechanical wire bonding process with a semiconductor fabrication-based TSV approach. Instead of attaching wires mechanically to bond pads, the invention forms conductive vias through the substrate using standard semiconductor processing techniques (etching, filling, planarization), achieving shorter paths and better electrical performance while maintaining manufacturability through established CMOS fabrication processes.

The patent introduces a fan-out structure as an intermediary component between the CIS die and DRAM die. This intermediate layer with its fan-out circuitry and TSVs acts as a buffer that absorbs the size mismatch, allowing standard-sized DRAM dies to be used without custom design modifications. The fan-out structure handles the size adaptation, simplifying the manufacturing of both the CIS and DRAM components.