CIS Device Gate Electrode Segmentation for Flicker Noise Reduction
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Solution Overview
Problem
Conductor-insulator-semiconductor (CIS) devices face challenges with flicker noise due to charge carrier trapping at the interface between the gate dielectric layer and the selectively-conductive channel, particularly at the high-defect-state STI corners, which are difficult to mitigate using existing etching and thermal processes without damaging existing structures or increasing complexity and cost.
Innovation Solution
The CIS device incorporates a gate electrode with peripheral segments that mask the STI corners, spacing the source/drain regions away from these corners, reducing charge carrier interactions and creating high-resistance paths, thereby lowering flicker noise through a cost-effective and low-complexity process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If existing etching and thermal processes are used to mitigate flicker noise at STI corners, then flicker noise is reduced, but existing structures are damaged or process complexity and cost increase
Solution Approach 1:
The gate electrode is designed with extended peripheral segments that proactively mask the STI corners before charge carrier trapping can occur. This preliminary geometric configuration prevents the harmful interaction between charge carriers and defect states at the STI corners, reducing flicker noise without requiring additional etching or thermal processing steps that would increase complexity
Solution Approach 2:
The invention converts the potentially harmful STI corner regions into beneficial elements by using the gate electrode's peripheral segments to mask these corners. The masking effect transforms the high-defect-state regions into low-noise zones, as the gate electrode structure itself becomes the protective element that prevents charge carrier trapping while maintaining device functionality
2Object-affected harmful factors
If existing etching and thermal processes are used to mitigate flicker noise at STI corners, then flicker noise is reduced, but existing structures are damaged
Solution Approach 1:
The gate electrode structure is designed to mask the STI corners, converting the potentially harmful high-defect-state regions into beneficial low-noise zones. This approach protects existing structures from damage while reducing flicker noise, as the gate electrode itself serves as the protective masking element rather than requiring aggressive etching or thermal processes that could compromise structure integrity
3Area of stationary object
If source/drain regions are placed close to STI corners, then device area is reduced, but charge carrier trapping increases and flicker noise increases
Solution Approach 1:
The gate electrode is segmented into peripheral segments that extend to mask the STI corners, creating distinct functional zones. This segmentation allows the source/drain regions to be positioned closer to the STI corners while the peripheral gate segments provide localized masking, reducing charge carrier trapping and flicker noise without requiring increased spacing that would enlarge the overall device area
Solution Approach 2:
The invention allows source/drain regions to be positioned near STI corners (maintaining compact area) while the gate electrode's peripheral segments convert the potentially harmful proximity to beneficial masking effect. The gate structure itself becomes the protective element that enables close positioning without increased flicker noise
Data Source
AI summary
A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.