CMOS Image Sensor Transfer Gate Masking for Dark Current Reduction
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Solution Overview
Problem
Conventional CMOS image sensor fabrication processes fail to effectively reduce dark current due to the shallower doped region formed under the transfer gate, which limits image contrast.
Innovation Solution
A CMOS image sensor process that involves forming a thickening layer, including a hard mask layer or composite layer, to create a transfer-gate pattern, allowing for deeper ion implantation of the PN junction without forming a doped region under the transfer gate, thereby reducing dark current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If ion implantation is performed with large implantation depth to form doped region of diode, then dark current is reduced, but a shallower doped region is formed under the gate which increases dark current
Solution Approach 1:
The patent divides the gate structure into multiple segments: the original gate and an additional thickening layer (first dielectric layer and first conductive layer) formed on top. This segmentation allows the implantation mask to extend beyond the original gate, enabling deeper ion implantation to form the diode doped region while preventing dopant diffusion under the gate, thus resolving the contradiction between achieving deep implantation and preventing shallower doped region formation.
Solution Approach 2:
The patent performs preliminary formation of the thickening layer (first dielectric layer and first conductive layer) on the gate before performing ion implantation. This preliminary action creates an extended mask structure that guides the ion implantation process, ensuring that dopants are implanted to the desired depth in the diode region while being blocked from forming shallower doped regions under the gate, thereby resolving the depth control precision issue.
2Productivity
If gate is exposed in ion implantation to ensure complete area exposure, then diode formation is complete, but shallower doped region forms under gate increasing dark current
Solution Approach 1:
The patent introduces an intermediary structure - the thickening layer comprising the first dielectric layer and first conductive layer - that acts as an extension of the gate mask. This intermediary allows the ion implantation to proceed completely over the diode area while simultaneously serving as a barrier that prevents dopants from forming shallower doped regions under the gate, thus resolving the contradiction between complete diode formation and dark current reduction.
3Length of stationary object
If implantation depth is larger than gate thickness, then deep doped region is formed, but shallower doped region forms beside it under gate
Solution Approach 1:
The patent segments the mask structure by adding the thickening layer (first dielectric layer and first conductive layer) on top of the gate. This segmentation creates a stepped mask configuration that allows ions to reach deep doped regions in the diode area while the extended mask portions prevent ions from creating shallower doped regions under the gate, thus resolving the positioning precision issue.
Solution Approach 2:
The patent adds a vertical dimension to the mask structure by forming the thickening layer on top of the gate. This dimensional change creates a three-dimensional mask configuration that provides both deep implantation capability and precise lateral positioning control, preventing shallower doped regions from forming under the gate while maintaining deep doped region formation in the diode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the dark current in CMOS image sensors, enhancing image contrast by ensuring the PN junction is formed deeply in the substrate without a doped region under the transfer gate.
Implementation Method 1
The thickening layer is defined to form a transfer-gate pattern, and then the transfer-gate pattern is used as an etching mask to pattern the gate material layer and form a transfer gate
Implementation Method 2
Ion implantation is then done to form a PN diode in the substrate with the transfer-gate pattern and the transfer gate as a mask
Data Source
AI summary
A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to form a transfer-gate pattern, and then the transfer-gate pattern is used as an etching mask to pattern the gate material layer and form a transfer gate. Ion implantation is then conducted to form a PN diode in the substrate with the transfer-gate pattern and the transfer gate as a mask.