cJTAG Interface Format Select Register for Debug Pin Count Reduction
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Solution Overview
Problem
The IEEE 1149.1 standard, or JTAG architecture, does not permit effective debug and testing of individual components on printed circuit boards, limiting the ability to test and debug JTAG compatible components mounted on these boards.
Innovation Solution
The cJTAG architecture extends the JTAG standard by providing a compact, low-pin-count interface that allows for advanced mode operations, enabling debug and test sequences to be sent to target systems, and includes adapters that convert standard JTAG signals into cJTAG signals, enabling communication using fewer signals and allowing for multiple protocols to operate independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the standard JTAG architecture is used, then the interface pin count is maintained at standard levels, but the ability to debug and test individual components on printed circuit boards is limited
Solution Approach 1:
The patent segments the JTAG interface functionality by separating the standard JTAG protocol handling from the extended debug capabilities. The boundary scan register is divided into functional segments that can be independently controlled, allowing selective activation of testing features without requiring additional pins. This segmentation enables the system to provide enhanced debug capability while maintaining the standard pin count.
Solution Approach 2:
The patent implements multi-functionality by designing the boundary scan register to serve both standard JTAG testing operations and extended individual component debug operations. The same physical interface and register structure are made universal to handle multiple protocols and testing modes, eliminating the need for additional pins while expanding debug capability.
2Adaptability or versatility
If the JTAG architecture is extended to enable individual component testing, then debug capability is improved, but the interface complexity increases
Solution Approach 1:
The patent applies the nesting principle by embedding the extended debug functionality within the existing JTAG architecture framework. The individual component testing capability is nested within the boundary scan register structure, which itself is nested within the standard JTAG protocol layering. This nested approach allows enhanced functionality to be integrated without adding interface complexity.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a format select register that mediates between the standard JTAG interface and the extended debug functionality. This intermediary allows the system to switch between different operating modes and protocols without requiring separate physical interfaces, thereby improving component testing capability while maintaining interface simplicity.
3Adaptability or versatility
If multiple protocols are allowed to operate independently, then adaptability is improved, but control complexity increases
Solution Approach 1:
The patent implements dynamics by making the protocol operation mode selectable and changeable through the format select register. The system can dynamically switch between standard JTAG protocol operation and extended multi-protocol operation based on the configuration state. This dynamic approach allows multiple protocols to operate independently when needed while maintaining simple single-protocol operation when sufficient, thereby improving adaptability without permanently increasing control complexity.
Data Source
AI summary
A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.