Compact JTAG Interface Pin Count Reduction
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Solution Overview
Problem
The IEEE 1149.1 standard, or JTAG architecture, does not permit effective debug and testing of individual components on printed circuit boards, limiting the ability to test and debug JTAG compatible components mounted on these boards.
Innovation Solution
The introduction of a Compact JTAG (cJTAG) architecture, which reduces the pin count of the interface between the debug test system and the target system, allowing for advanced mode operations through inert JTAG data scan sequences and optimized scan message formats, enabling more efficient data exchanges and extended functionality beyond standard JTAG capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard JTAG architecture is used, then pin count is maintained at standard levels, but testing and debugging capabilities of individual components are limited
Solution Approach 1:
The patent segments the communication protocol into distinct packet types (control packets with address and data segments) that can be selectively processed. This allows the system to handle multiple testing functions through structured data packets rather than requiring separate physical pins for each function.
Solution Approach 2:
The patent implements a universal communication interface where a single communication link can perform multiple functions (testing, debugging, data transfer) by using different packet formats and protocols. This eliminates the need for additional dedicated pins for each testing capability.
2Adaptability or versatility
If additional pins are added to enhance testing capabilities, then advanced debug and testing functions are enabled, but device complexity and pin count increase
Solution Approach 1:
The patent creates a universal test access port that can perform advanced debugging and testing functions through software-controlled protocols over the existing pins. The system uses standardized packet structures that can carry various types of test data, control commands, and debug information, making the existing pin infrastructure multi-functional.
Solution Approach 2:
The patent introduces a protocol layer and packet structure as an intermediary between the physical pins and the testing functions. This intermediary layer enables advanced capabilities by encoding multiple functions within the data packets, allowing the system to achieve more functionality without adding physical pins.
3Device complexity
If pin count is reduced, then interface simplicity is improved, but data exchange performance may be compromised
Solution Approach 1:
The patent employs periodic clocking and structured packet transmission to optimize data exchange over the reduced pin interface. By organizing data into periodic packets with clear delimiters and using synchronized clocking, the system maintains high data exchange efficiency despite using fewer pins.
Solution Approach 2:
The patent changes the parameters of data transmission by using variable-length packets, different data formats, and adjustable baud rates. This allows the system to optimize data exchange performance for different testing scenarios while maintaining a simple pin interface, effectively compensating for the reduced pin count through protocol optimization.
Data Source
AI summary
A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system. The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active.