cJTAG Link ID Assignment for Component Debug
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Solution Overview
Problem
The IEEE 1149.1 standard, also known as the JTAG architecture, does not permit effective debug and testing of individual components mounted on a printed circuit board, limiting the ability to test and debug these components beyond board-level interconnect testing.
Innovation Solution
The cJTAG architecture extends the JTAG standard by reducing the number of communication signals, allowing for advanced mode operations that enable debug and test sequences through a compact interface, using fewer pins and optimizing data transfer by serializing signals, thereby enabling component-level testing while maintaining compatibility with the underlying JTAG protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the IEEE 1149.1 standard JTAG architecture is used for testing, then board-level interconnect testing can be performed, but component-level debug and testing of individual components mounted on the printed circuit board is not permitted
Solution Approach 1:
The patent segments the testing capability by introducing a controller that can selectively isolate and test individual components (I/O devices) on the printed circuit board independently from other components. This allows component-level testing while maintaining the overall JTAG architecture, resolving the contradiction between testing versatility and interface complexity.
Solution Approach 2:
The patent introduces a controller as an intermediary between the JTAG test access port and the I/O devices on the printed circuit board. This controller provides the additional functionality needed for component-level testing while shielding the standard JTAG interface from complexity, allowing versatile testing without increasing interface complexity.
2Productivity
If multiple I/O devices are connected to the same link ID, then resource utilization is improved, but address conflicts and testing ambiguity occur
Solution Approach 1:
The patent implements dynamic address assignment where the controller can change the link ID of a specific I/O device on demand. This allows the system to adaptively allocate unique addresses during testing operations, resolving address conflicts while maintaining high resource utilization when devices share link IDs for non-critical operations.
Solution Approach 2:
The patent changes the link ID parameter of I/O devices dynamically based on testing requirements. By modifying the link ID value assigned to a device, the system can resolve address conflicts and ensure unique identification during component-level testing, while allowing multiple devices to share link IDs for resource optimization in other scenarios.
3Reliability
If link ID assignment is deferred to after device isolation, then address conflicts are avoided, but additional testing steps are required
Solution Approach 1:
The patent performs preliminary device isolation using isolation patterns before link ID assignment. By isolating the target I/O device first, the system ensures accurate and unambiguous address assignment. The time overhead is minimized by efficiently implementing the isolation step, which enables reliable component-level testing that would otherwise require multiple retry attempts due to address conflicts.
Data Source
AI summary
An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.