Clad Gate Wiring for LCD Driving Circuit
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Solution Overview
Problem
The challenge lies in implementing low-resistance wiring for large-scale liquid crystal display panels, which is complicated due to signal delay and disconnection issues, especially when using materials that resist oxidation and prevent disconnects during fabrication.
Innovation Solution
A clad structure is formed by creating a second gate wiring using a non-reactive conductive material to cover a low-resistance first gate wiring, ensuring the first gate wiring is protected from developers during the doping process, thereby maintaining low resistance and preventing signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low-resistance conductive material is used for the first gate wiring, then the electrical resistance is reduced, but the wiring becomes susceptible to oxidation and disconnection during fabrication
Solution Approach 1:
The patent applies a composite structure by forming a second gate wiring layer comprising a non-reactive conductive material over the first gate wiring layer. This composite structure combines the low-resistance properties of the first layer with the oxidation resistance of the second layer, solving both the electrical performance and reliability requirements simultaneously.
Solution Approach 2:
The second gate wiring acts as an intermediary protective layer between the low-resistance first gate wiring and the oxidizing environment during fabrication. This intermediary layer prevents direct contact between the reactive conductive material and oxidizing agents, thereby preventing oxidation and disconnection while maintaining the electrical functionality of the underlying layer.
2Object-affected harmful factors
If a clad structure with second gate wiring is formed over the first gate wiring, then oxidation resistance is improved, but the device structure becomes more complex
Solution Approach 1:
The second gate wiring layer serves multiple functions simultaneously: it provides oxidation resistance, acts as a protective barrier against disconnection, and maintains electrical conductivity. By consolidating these multiple protective and functional roles into a single structural element, the patent reduces overall device complexity while achieving the desired oxidation resistance.
Solution Approach 2:
The patent merges the protective function against oxidation with the electrical conduction function by integrating the second non-reactive conductive material layer directly over the first low-resistance wiring layer. This merging creates a unified gate wiring structure that simultaneously provides both protection and electrical functionality, thereby simplifying the overall device architecture.
Data Source
AI summary
A method of fabricating a liquid crystal display device includes providing a first substrate having a first region and a second region; forming an active pattern in the first and second regions of the first substrate; forming a first insulation film on the first substrate; forming a first gate electrode with a low-resistance conductive material on an upper portion of the active pattern; forming a second gate electrode to completely cover the first gate electrode on an exposed portion of the first gate electrode; forming N type source and drain regions in the active pattern of the first region by doping an n+ impurity ion; forming P type source and drain regions in the active pattern of the second region by doping a p+ impurity ion; forming a second insulation film on the first substrate; forming N type source and drain electrodes electrically connected with the N type source and drain regions on the first region and forming P type source and drain electrodes electrically connected with the P type source and drain regions on the second region; and attaching the first and second substrates. A low-resistance wiring can be implemented on a large-scale liquid crystal display panel by forming a second gate wiring of a clad structure at an upper portion of a low-resistance first gate wiring.


