Cladded Quantum Dot Gate for Nonvolatile Memory Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional quantum dot gate memory devices face challenges with small retention time and fluctuations in electrical characteristics due to uncertainties in dot size, placement, and separation, leading to inadequate control over inter-dot tunneling and gate leakage currents.
Innovation Solution
The use of cladded quantum dots with appropriate core and cladding thicknesses, assembled on the transport channel of a field-effect transistor (FET) to form a floating gate, along with an asymmetric coupled quantum well transport channel, enhances retention time and control over inter-dot tunneling, and reduces gate leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional quantum dots are used in gate structure, then device complexity is reduced, but retention time is small and electrical characteristics fluctuate
Solution Approach 1:
The patent implements a nested structure where quantum dots are embedded within an insulating material matrix, forming a composite gate structure. The quantum dots are positioned within tunnel oxide layers, creating a hierarchical arrangement that enhances charge retention while maintaining structural integrity. This nesting approach allows the quantum dots to be confined in specific regions, improving retention time without requiring overly complex external control mechanisms.
Solution Approach 2:
The patent employs composite materials by combining quantum dots with insulating materials (such as silicon oxide or silicon nitride) to form a composite gate structure. This composite approach leverages the charge-trapping capability of quantum dots while using the insulating material to provide structural support and electrical isolation. The composite structure enhances retention time and stabilizes electrical characteristics without significantly increasing device complexity.
2Reliability
If quantum dot size and placement are not controlled, then manufacturing is simpler, but inter-dot tunneling and gate leakage currents increase
Solution Approach 1:
The patent applies preliminary action by pre-forming the insulating material matrix before introducing quantum dots into specific positions. The tunnel oxide layers are deposited and structured in advance, creating predefined sites where quantum dots will be embedded. This preliminary structuring ensures that quantum dots are placed at controlled intervals, preventing inter-dot tunneling and reducing gate leakage currents while maintaining manufacturing feasibility.
Solution Approach 2:
The insulating material serves as an intermediary between quantum dots, providing physical separation and electrical isolation. The tunnel oxide layers act as intermediary barriers that prevent direct interaction between adjacent quantum dots, thereby controlling inter-dot tunneling. This intermediary approach allows quantum dots to be positioned closer together for higher density while maintaining electrical independence, resolving the conflict between manufacturing simplicity and tunneling control.
3Area of stationary object
If quantum dots are placed closer together, then device area is reduced, but inter-dot tunneling increases
Solution Approach 1:
The insulating material matrix serves as an intermediary barrier between closely spaced quantum dots, preventing direct tunneling while allowing compact arrangement. The tunnel oxide layers provide electrical isolation that enables quantum dots to be positioned at reduced spacing without increasing inter-dot tunneling current. This intermediary approach allows the memory device to achieve high storage density in reduced area while maintaining electrical stability.
Solution Approach 2:
The patent applies local quality by providing different material properties in different regions of the gate structure. The insulating material is specifically positioned between quantum dots to provide localized electrical isolation, while allowing quantum dots to be closely spaced in the lateral direction for high density. This localized differentiation enables reduced device area without increasing harmful inter-dot tunneling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved write and read characteristics, longer retention time, and reduced fluctuations in device performance, enabling scalable nonvolatile memory devices with enhanced multi-bit storage capabilities.
Implementation Method 1
an asymmetric coupled quantum well transport channel that enhances the retention time in a nonvolatile memory by increasing the 'effective' separation between channel charge (located in the lower quantum well) and the quantum dots
Implementation Method 2
The cladding maintains a sufficient separation between Si nanodots, and between dots, transport channel and the control gate; thereby controlling the inter-dot tunneling
Data Source
AI summary
The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET.