Cladding Layer Epitaxy for Heterogeneous Integration on Silicon
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Solution Overview
Problem
The integration of III-V compound materials and germanium in transistor channels is hindered by lattice mismatch with silicon, leading to defect formation and impaired electrical performance.
Innovation Solution
A non-planar semiconductor device with a channel region featuring a low band-gap cladding material, where the cladding material is epitaxially grown around nanowires with a different cross-sectional shape than the core, allowing for coalescence and reducing defect density, thereby enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V compound materials and germanium are integrated in transistor channels, then carrier mobility and drive current performance are improved, but lattice mismatch with silicon causes defect formation and impaired electrical performance
Solution Approach 1:
A silicon germanium cladding layer is introduced as an intermediary between the silicon substrate and the III-V compound material channel. This cladding layer has a lattice constant that gradually transitions from silicon to the III-V material, reducing the lattice mismatch and preventing defect formation during the integration process
Solution Approach 2:
The lattice constant of the cladding layer is adjusted by varying the germanium content to create a gradient that matches the lattice parameters of both the silicon substrate and the III-V channel material. This parameter change enables smooth integration without defects
2Reliability
If cladding layers are grown around nanowires, then defect density is reduced and current capacity increases, but the cross-sectional shape mismatch between nanowires and cladding layers creates manufacturing complexity
Solution Approach 1:
The cladding layer growth process is made dynamic by allowing the cladding to conform to the nanowire shape during epitaxial growth. The cross-sectional shape of the cladding layer is designed to evolve from a circular nanowire template to a rectangular final shape, accommodating both shapes during the transition
Solution Approach 2:
Different regions of the cladding layer are designed with different cross-sectional shapes to match the local geometry of the nanowire at different stages of growth, enabling defect-free integration while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher current capacity and performance by allowing the cladding layers to merge into a single monolithic transistor with reduced resistance, overcoming the limitations of lattice mismatch and defect formation.
Implementation Method 1
the cladding material is epitaxially grown around nanowires with a different cross-sectional shape than the core
Data Source
AI summary
An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.